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參數(shù)資料
| 型號(hào)： | W28J161TB90L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封裝： | 8 X 8 MM, 0.75 MM PITCH, TFBGA-48 |
| 文件頁(yè)數(shù)： | 30/43頁(yè) |
| 文件大?。?/td> | 1333K |
| 代理商： | W28J161TB90L |
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W28J161B/T
- 36 -
Alternative #CE - Controlled Writes(1)
VDD = 2.7V to 3.6V, TA = -40 ° C to +85° C
PARAMETER
SYM.
MIN.
MAX.
UNIT
Write Cycle Time
tAVAV
90
nS
#RESET High Recovery to #CE Going Low (note 2)
tPHEL
1
S
#WE Setup to #CE Going Low
tWLEL
0
nS
#CE Pulse Width
tELEH
65
nS
#WP VIH Setup to #CE Going High (note 2)
tSHEH
100
nS
VPP Setup to #CE Going High (note 2)
tVPEH
100
nS
Address Setup to #CE Going High (note 3)
tAVEH
50
nS
Data Setup to #CE Going High (note 3)
tDVEH
50
nS
Data Hold from #CE High
tEHDX
0
nS
Address Hold from #CE High
tEHAX
0
nS
#WE Hold from #CE High
tEHWH
0
nS
#CE Pulse Width High
tEHEL
25
nS
#CE High to SR.7 Going "0"
tEHR0
100
nS
Write Recovery before Read
tEHGL
0
nS
VPP Hold from Valid SRD (note 2, 4)
tQVVL
0
nS
#WP VIH Hold from Valid SRD (note 2, 4)
tQVSL
0
nS
Notes:
1. In systems where #CE defines the write pulse width (within a longer #WE timing waveform), all setup, hold, and inactive #WE
times should be measured relative to the #CE waveform.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN and DIN for block erase, full chip erase, word write or lock-bit configuration.
4. VPP should be held at VPPH1/2 until determination of block erase, full chip erase, word write or lock-bit configuration success
(SR.1/3/4/5 = 0).
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