參數(shù)資料
型號: W28J161TB90L
廠商: WINBOND ELECTRONICS CORP
元件分類: PROM
英文描述: 1M X 16 FLASH 3V PROM, 90 ns, PBGA48
封裝: 8 X 8 MM, 0.75 MM PITCH, TFBGA-48
文件頁數(shù): 40/43頁
文件大?。?/td> 1333K
代理商: W28J161TB90L
W28J161B/T
- 6 -
5. PIN CONFIGURATIONS
A
B
C
D
E
F
A13
A14
A15
A16
VDD
VSS
A11
A8
Vpp
#WP
A19
A7
A4
A10
#WE
#RESET
A18
A17
A5
A2
A12
A9
NC
A6
A3
A1
DQ14
DQ15
DQ7
DQ5
DQ6
DQ13
DQ11
DQ12
DQ4
VDD
DQ10
DQ1
#OE
VSS
DQ0
DQ9
DQ3
DQ2
DQ8
#CE
A0
1
2
3
45
67
8
0.75mm pitch
48-Ball TFBGA
Pinout
8 x 8 mm
TOP VIEW
Figure 2. 0.75 mm pitch TFBGA 48-Ball Pinout
6. PIN DESCRIPTION
SYM.
TYPE
NAME AND FUNCTION
A0
A19
INPUT
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
A15
A19: Main Block Address.
A12
A19: Boot and Parameter Block Address.
DQ0
DQ15
INPUT/
OUTPUT
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data during
memory array, status register and identifier code read cycles. Data pins float to high impedance
when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle.
#CE
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers.
#CE-high deselects the device and reduces power consumption to standby levels.
#RESET
INPUT
RESET: Resets the device internal automation. #RESET-high enables normal operation. When
driven low, #RESET inhibits write operations which provides data protection during power
transitions. Exit from reset mode sets the device to read array mode. #RESET must be VIL during
power-up.
#OE
INPUT
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
#WE
INPUT
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on
the rising edge of the #WE pulse.
#WP
INPUT
WRITE PROTECT: When #WP is VIL, boot blocks cannot be written or erased. When #WP is VIH,
locked boot blocks can not be written or erased. #WP is not affected parameter and main blocks.
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