參數(shù)資料
型號(hào)： W28J161TB90L
廠商： WINBOND ELECTRONICS CORP
元件分類： PROM
英文描述： 1M X 16 FLASH 3V PROM, 90 ns, PBGA48
封裝： 8 X 8 MM, 0.75 MM PITCH, TFBGA-48
文件頁(yè)數(shù)： 33/43頁(yè)
文件大?。?/td> 1333K
代理商： W28J161TB90L
W28J161B/T
Publication Release Date: April 7, 2003
- 39 -
Revision A4
Block Erase, Full Chip Erase, Word Write And Lock-Bit Configuration
Performance(3)
VDD = 2.7V to 3.6V, TA = -40 ° C to +85° C
VPP = 2.7V 3.6V
VPP = 11.7V 12.3V
SYM.
PARAMETER
NOTE
Min. Typ.(1) Max.
UNIT
32k word Block
2
33
200
20
S
tWHQV1
tEHQV1
Word Write Time
4k word Block
2
36
200
27
S
32k word Block
2
1.1
4
0.66
S
Block Write Time
(In word mode)
4k word Block
2
0.15
0.5
0.12
S
32k word Block
2
1.2
6
0.9
S
tWHQV2
tEHQV2
Block Erase Time
4k word Block
2
0.6
5
0.5
S
Full Chip Erase Time
2
42
210
32
S
tWHQV3
tEHQV3
Set Lock-Bit Time
2
56
200
42
S
tWHQV4
tEHQV4
Clear Block Lock-Bits Time
2
1
5
0.69
S
tWHR11
tEHR11
Word Write Suspend Latency Time to
Read
4
6
15
6
15
S
tWHR12
tEHR12
Block Erase Suspend Latency Time to
Read
4
16
30
16
30
S
tERES
Latency Time from Block Erase
Resume Command to Block Erase
Suspend Command
5
600
S
Notes:
1. Typical values measured at TA = +25
° C and VDD = 3.0V, VPP = 3.0V or 12.0V. Assumes corresponding lock-bits are not set.
Subject to change based on device characterization.
2. Excludes system-level overhead.
3. Sampled but not 100% tested.
4. A latency time is required from issuing suspend command(#WE or #CE going high) until SR.7 going "1".
5. If the time between writing the Block Erase Resume command and writing the Block Erase Suspend command is shorter than
tERES and both commands are written repeatedly, a longer time is required than standard block erase until the completion of
the operation.
相關(guān)PDF資料
PDF描述
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