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參數(shù)資料
| 型號： | W25P20-VSNI-G |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 2M X 1 FLASH 2.7V PROM, PDSO8 |
| 封裝： | 0.150 INCH, GREEN, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 3/35頁 |
| 文件大?。?/td> | 1405K |
| 代理商： | W25P20-VSNI-G |
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W25P10, W25P20 AND W25P40
Publication Release Date: November 28, 2005
- 11 -
Revision M
7.1.6
Status Register Memory Protection
STATUS REGISTER
(1)
W25P40 (4M-BIT) MEMORY PROTECTION
BP2
BP1
BP0
SECTOR(S)
ADDRESSES
DENSITY (KB)
PORTION
0
NONE
0
1
7
070000h - 07FFFFh
512K-bit
Upper 1/8
0
1
0
6 and 7
060000h - 07FFFFh
1M-bit
Upper 1/4
0
1
4 thru 7
040000h - 07FFFFh
2M-bit
Upper 1/2
1
x
ALL
000000h - 07FFFFh
4M-bit
ALL
STATUS REGISTER
(1)
W25P20 (2M-BIT) MEMORY PROTECTION
BP2
BP1
BP0
SECTOR(S)
ADDRESSES
DENSITY (KB)
PORTION
x
0
NONE
x
0
1
3
030000h - 03FFFFh
512K-bit
Upper 1/4
x
1
0
2 and 3
020000h - 03FFFFh
1M-bit
Upper 1/2
x
1
ALL
000000h - 03FFFFh
2M-bit
ALL
STATUS REGISTER
(1)
W25P10 (1M-BIT) MEMORY PROTECTION
BP2
BP1
BP0
SECTOR(S)
ADDRESSES
DENSITY (KB)
PORTION
x
0
x
NONE
x
1
0
NONE
x
1
ALL
000000h - 01FFFFh
1M-bit
ALL
Note:
1. x = don’t care
7.2
INSTRUCTIONS
The instruction set of the W25P10/20/40 consists of twelve basic instructions that are fully controlled
through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip
Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the
DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes,
data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed
with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in
figures 4 through 16. All read instructions can be completed after any clocked bit. However, all
instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a
full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects
the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or
when the Status Register is being written, all instructions except for Read Status Register will be
ignored until the program or erase cycle has completed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W25Q128BVFAP | 128M X 1 SPI BUS SERIAL EEPROM, PDSO16 |
| W25Q128BVEIP | 128M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| W25Q128BVFIP | 128M X 1 SPI BUS SERIAL EEPROM, PDSO16 |
| W25Q16CLSFIP | 16M X 1 SPI BUS SERIAL EEPROM, PDSO16 |
| W25Q16CLDAIG | 16M X 1 SPI BUS SERIAL EEPROM, PDIP8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W25P20VSNIG T&R | 功能描述:IC FLASH 2MBIT 40MHZ 8SOIC RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:SpiFlash® 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| W25P222A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P222A-4 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P222A-4A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P222AD-4 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
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