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參數(shù)資料
| 型號： | W25P20-VSNI-G |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 2M X 1 FLASH 2.7V PROM, PDSO8 |
| 封裝： | 0.150 INCH, GREEN, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 10/35頁 |
| 文件大?。?/td> | 1405K |
| 代理商： | W25P20-VSNI-G |
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W25P10, W25P20 AND W25P40
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7.2.9
Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes of data to be programmed at memory
locations previously erased to all 1s (FFh). A Write Enable instruction must be executed before the
device will accept the Page Program Instruction (Status Register bit WEL must equal 1). The
instruction is initiated by driving the /CS pin low then shifting the instruction code “02h” followed by a
24-bit address (A23-A0) and at least one data byte, into the DI pin. The /CS pin must be driven low for
the entire length of the instruction while data is being sent to the device. The Page Program instruction
sequence is shown in figure 10.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address
bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceed the
remaining page length, the addressing will wrap to the beginning of the page. Less than 256 bytes can
be programmed without having any effect on other bytes within the same page. If more than 256 bytes
are sent to the device the addressing will wrap to the beginning of the page and overwrite previously
sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last
byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS
is driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See
AC Characteristics). While the Page Program cycle is in progress, the Read Status Register
instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during
the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept
other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit
in the Status Register is cleared to 0. The Page Program instruction will not be executed if the
addressed page is protected by the Block Protect (BP2, BP1, BP0) bits (see Status Register Memory
Protection table).
Figure 10. Page Program Instruction Sequence Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W25Q128BVFAP | 128M X 1 SPI BUS SERIAL EEPROM, PDSO16 |
| W25Q128BVEIP | 128M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| W25Q128BVFIP | 128M X 1 SPI BUS SERIAL EEPROM, PDSO16 |
| W25Q16CLSFIP | 16M X 1 SPI BUS SERIAL EEPROM, PDSO16 |
| W25Q16CLDAIG | 16M X 1 SPI BUS SERIAL EEPROM, PDIP8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W25P20VSNIG T&R | 功能描述:IC FLASH 2MBIT 40MHZ 8SOIC RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:SpiFlash® 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| W25P222A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P222A-4 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P222A-4A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P222AD-4 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
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