參數(shù)資料
型號(hào)： VG26VS17405DT-5
廠商： VANGUARD INTERNATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： 4M X 4 EDO DRAM, 50 ns, PDSO24
封裝： 0.300 INCH, PLASTIC, TSOP2-26/24
文件頁(yè)數(shù)： 6/27頁(yè)
文件大小： 253K
代理商： VG26VS17405DT-5
Document:1G5-0124
Rev.1
Page 14
VIS VG26(V)(S)17405
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Notes :
1. AC measurements assume tT = 2ns.
2. An initial pause of 100
is required after power up, and it followed by a minimum of eight
initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal
refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required.
3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
4. All the VCC and VSS pins shall be supplied with the same voltages.
5. tRAS(min) = tRWD(min)+tRWL(min)+tT in read-modify-write cycle.
6. tCAS(min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle.
7. tASC(min), tRCS(min), tWCS(min), and tRPC are determined by the falling edge of CAS .
8. tRCD(max) is specified as a reference point only, and tRAC(max) can be met with the tRCD(max) limit.
Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit.
9. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit.
Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit.
10. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the rising edge of CAS .
11. VIH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition
time is measured between VIH and VIL.
12. Assumes that tRCD
tRCD(max) and tRAD
tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
13. Assumes that
(max) and
(max).
14. Access time is determined by the maximum of tAA, tCAC, tCPA.
15. Assumes that
(max) and
(max).
16. Either tRCH or tRRH must be satisfied for a read cycle.
17. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high
impedance). tOFF is determined by the later rising edge of RAS or CAS.
18. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If
(min), the cycle is an early write cycle and the
data out will remain open circuit (high impedance) throughout the entire cycle. If
(min),
(min) and
(min), the cycle is a read-modify-write and
the data output will contain data read from the selected cell. If neither of the above sets of conditions
is satisfied, the condition of the data output (at access time) is indeterminate.
19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in a
delayed write or a read-modify-write cycle.
20. tRASP defines RAS pulse width in EDO page mode cycles.
s
≤
t
RCD
t
RCD
≥
t
RAD
t
RAD
≤
t
RCD
t
RCD
≤
t
RAD
t
RAD
≥
t
WCS
t
WCS
≥
t
RWD
t
RWD
≥
t
CWD
t
CWD
≥
t
AWD
t
AWD
≥
t
CPW
t
CPW
≥
相關(guān)PDF資料
PDF描述
VG26VS17405J-5 4M X 4 EDO DRAM, 50 ns, PDSO24
VG36128161BFL-7H 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54
VG36128161BT-7H 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
VG36128161BFL-7L 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54
VG95234E32-5P1X 2 CONTACT(S), ALUMINUM ALLOY, MALE, MIL SERIES CONNECTOR, CLAMP AND CRIMP, PLUG
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
VG26VS17405DT-6 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x4 EDO Page Mode DRAM
VG26VS17405EJ-5 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x4 EDO Page Mode DRAM
VG26VS17405EJ-6 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x4 EDO Page Mode DRAM
VG26VS17405ET-5 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x4 EDO Page Mode DRAM
VG26VS17405ET-6 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x4 EDO Page Mode DRAM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*