參數(shù)資料
型號(hào): VG26VS17405DT-5
廠商: VANGUARD INTERNATIONAL SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 4M X 4 EDO DRAM, 50 ns, PDSO24
封裝: 0.300 INCH, PLASTIC, TSOP2-26/24
文件頁(yè)數(shù): 26/27頁(yè)
文件大小: 253K
代理商: VG26VS17405DT-5
Document:1G5-0124
Rev.1
Page 8
VIS VG26(V)(S)17405
4,194,304 x 4 - Bit
CMOS Dynamic RAM
DC Characteristics ; 3.3 - Volt Version
(Ta = 0 to 70°C, VCC = + 3.3V
%, VSS = 0V)
Parameter
Symbol
Test Conditions
VG26(V)(S)17405
Unit
Notes
-5
-6
Min
Max
Min
Max
Operating current
ICC1
RAS cycling
CAS, cycling
tRC = min
-
120
-
110
mA
1, 2
Standby
Current
LOW
power
S-version
ICC2
LVTTL interface
RAS, CAS = VIH
Dout = High-Z
-
0.5
-
0.5
mA
CMOS interface
RAS,
-0.2V
Dout = High-Z
-
0.15
-
0.15
mA
Standard
power
version
LVTTL interface
RAS, CAS = VIH
Dout = High-Z
-
2
-
2
mA
CMOS interface
RAS,
-0.2V
Dout = High-Z
-
0.5
-
0.5
mA
RAS- only refresh current
ICC3
RAS cycling, CAS = VIH
tRC = min
-
120
-
110
mA
1, 2
EDO page mode current
ICC4
tPC = min
-
90
-
80
mA
1, 3
CAS- before- RAS refresh
current
ICC5
tRC = min
RAS, CAS cycling
-
120
-
110
mA
1, 2
Self- refresh current
(S-Version)
ICC8
-
250
-
250
CAS- before- RAS long
refresh current
(S-Version)
ICC9
Standby: VCC-
CAS before RAS refresh:
2048 cycles / 128ms
RAS, CAS:
VCC-
(max)
Dout = High-Z,
-
300
-
300
10
±
CASV
CC
CASV
CC
t
RASS
100
s
A
0.2V
RAS
0VV
IL
0.2V
≤≤
0.2VV
IH
V
IH
≤≤
t
RAS
300ns
A
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