參數(shù)資料
型號: VG26VS17405DT-5
廠商: VANGUARD INTERNATIONAL SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 4M X 4 EDO DRAM, 50 ns, PDSO24
封裝: 0.300 INCH, PLASTIC, TSOP2-26/24
文件頁數(shù): 3/27頁
文件大?。?/td> 253K
代理商: VG26VS17405DT-5
Document:1G5-0124
Rev.1
Page 11
VIS VG26(V)(S)17405
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Read Cycle
Write Cycle
Read- Modify- Write Cycle
Parameter
Symbol
VG26(V)(S)17405
Unit
Notes
-5
-6
Min
Max
Min
Max
Access time from RAS
tRAC
-
50
-
60
ns
12
Access time from CAS
tCAC
-
13
-
15
ns
13, 14
Access time from column address
tAA
-
25
-
30
ns
14, 15
Access time from OE
tOEA
-
12
-
15
ns
Read command setup time
tRCS
0
-
0
-
ns
7
Read command hold time to CAS
tRCH
0
-
0
-
ns
10, 16
Read command hold time to RAS
tRRH
10
-
10
-
ns
16
Output buffer turn-off time
tOFF
0
12
0
15
ns
17
Output buffer turn-off time from OE
tOEZ
0
12
0
15
ns
17
Parameter
Symbol
VG26(V)(S) 17405
Unit
Notes
-5
-6
Min
Max
Min
Max
Write command setup time
tWCS
0
-
0
-
ns
7, 18
Write command hold time
tWCH
8
-
10
-
ns
Write command pulse width
tWP
8
-
10
-
ns
Write command to RAS lead time
tRWL
13
-
15
-
ns
Write command to CAS lead time
tCWL
8
-
10
-
ns
Data-in setup time
tDS
0
-
0
-
ns
19
Data-in hold time
tDH
8
-
10
-
ns
19
WE to Data-in delay
tWED
10
-
10
-
ns
Parameter
Symbol
VG26(V)(S) 17405
Unit
Notes
-5
-6
Min
Max
Min
Max
Read-modify- write cycle time
tRWC
108
-
133
-
ns
RAS to WE delay time
tRWD
64
-
77
-
ns
18
CAS to WE dealy time
tCWD
26
-
32
-
ns
18
Column address to WE delay time
tAWD
39
-
47
-
ns
18
OE hold time from WE
tOEH
8
-
10
-
ns
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