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參數(shù)資料
| 型號： | VDP3108PR |
| 英文描述： | Consumer IC |
| 中文描述： | 消費性IC |
| 文件頁數(shù)： | 42/72頁 |
| 文件大?。?/td> | 597K |
| 代理商： | VDP3108PR |
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VDP 31xxB
PRELIMINARY DATA SHEET
42
Micronas
Name
Default
Function
FP Sub-
address
Scaler Control Register
h
’
40
scaler mode register
bit[1:0]
scaler mode
0
1
2
3
reserved, set to 0
scaler update
0
start scaler update command,
when the registers are updated the bit is set to 1
linear scaling mode
nonlinear scaling mode,
’
panorama
’
nonlinear scaling mode,
’
waterglass
’
reserved
bit[10:2]
bit[11]
0
scmode
pano
h
’
41
luma offset register
bit[6:0]
luma offset 0..127
ITU-R output format:
CVBS output format:
57
4
this register is updated when the scaler mode register is written
57
yoffs
h
’
42
active video length for 1-h FIFO
bit[11:0]
length in pixels
this register is updated when the scaler mode register is written
1080
fflim
h
’
43
scaler1 coefficient, this scaler is compressing the signal.
For compression by a factor c the value c*1024 is required.
bit[11:0]
allowed values from 1024..4095
this register is updated when the scaler mode register is written
1024
scinc1
h
’
44
scaler2 coefficient, this scaler is expanding the signal.
For expansion by a factor c the value 1/c*1024 is required.
bit[11:0]
allowed values from 256..1024
this register is updated when the scaler mode register is written
1024
scinc2
h
’
45
scaler1/2 nonlinear scaling coefficient
this register is updated when the scaler mode register is written
0
scinc
h
’
47
–
h
’
4b
scaler1 window controls, see table
5 12-bit registers for control of the nonlinear scaling
this register is updated when the scaler mode register is written
0
scw1_0
–
4
h
’
4c
–
h
’
50
scaler2 window controls see table
5 12-bit registers for control of the nonlinear scaling
this register is updated when the scaler mode register is written
0
scw2_0
–
4
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