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參數(shù)資料
| 型號(hào)： | VDP3108PR |
| 英文描述： | Consumer IC |
| 中文描述： | 消費(fèi)性IC |
| 文件頁(yè)數(shù)： | 37/72頁(yè) |
| 文件大?。?/td> | 597K |
| 代理商： | VDP3108PR |
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VDP 31xxB
PRELIMINARY DATA SHEET
37
Micronas
Name
Default
Function
Mode
Number
of bits
I
2
C sub
address
TIMING
h
’
67
9
w v
vertical blanking start
bit [8:0]
0..511
first line of vertical blanking
305
VBST
h
’
77
9
w v
vertical blanking stop
bit [8:0]
0..511
last line of vertical blanking
25
VBSO
h
’
73
9
w v
start of Black Level Expander measurement
bit [8:0]
0..511
first line of measurement, stop with first
line
of vertical blanking
30
AVST
h
’
5f
9
w v
bit [8:0] free running field period = (value
4) lines
0
STIMP
HORIZONTAL DEFLECTION
h
’
7a
9
w v
adjustable delay of PLL2, clamping, and blanking (relative to
front sync)
adjust clamping pulse for analog RGB input
bit [8:0]
–
256..+255
8
μ
s
–
141
POFS2
h
’
76
9
w v
adjustable delay of flyback, main sync, csync and analog RGB
(relative to PLL2)
adjust horizontal drive or csync
bit [8:0]
–
256..+255
8
μ
s
0
POFS3
h
’
7e
9
w v
adjustable delay of main sync (relative to flyback)
adjust horizontal position for digital picture
bit [8:0]
20 steps
1
μ
s
120
HPOS
h
’
5b
9
w/r
start of horizontal blanking
bit [8:0]
0..511
1
HBST
h
’
57
9
w/r
end of horizontal blanking
bit [8:0]
0..511
48
HBSO
h
’
6a
h
’
6e
h
’
72
9
9
9
w v
w v
w v
PLL2/3 filter coefficients, 1of5 bit code (n
bit [5:0]
proportional coefficient PLL3, 2
–
n
–
1
bit [5:0]
proportional coefficient PLL2, 2
–
n
–
1
bit [5:0]
integral coefficient PLL2, 2
–
n
–
5
set bit number)
2
1
2
PKP3
PKP2
PKI2
h
’
15
16
w/r
horizontal drive and vertical signal control register
bit [5:0]
0..63
horizontal drive pulse duration in s
(internally limited to 4..61)
bit [6]
0/1
disable/enable horizontal PLL2 and PLL3
bit [7]
0/1
1: disable horizontal drive pulse during
flyback
bit [8]
0/1
reserved, set to
’
0
’
bit [9]
0/1
enable/disable ultra black blanking
bit [10]
0/1
0: all outputs blanked
1: normal mode
bit [11]
0/1
enable/disable clamping for analog RGB
input
bit [12]
0/1
disable/enable vertical free running mode
(FIELD is set to field2, no interlace)
bit [13]
0/1
enable/disable vertical protection
bit [14]
0/1
internal/external (under VPC control)
start of vertical and E/W signal
bit [15]
0/1
disable/enable phase shift of display clock
32
0
0
0
1
0
0
0
0
1
HDRV
EHPLL
EFLB
DUBL
EBL
DCRGB
SELFT
DVPR
XDEFL
DISKA
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|---|---|
| VDP3112B | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Processor Family |
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