
PRELIMINARY DATA SHEET
VDP 31xxB
41
Micronas
Name
Default
Function
FP Sub-
address
DVCO
h
’
f8
crystal oscillator center frequency adjust,
–
2048 ... 2047
–
720
dvco
h
’
f9
crystal oscillator center frequency adjustment value for line lock mode,
true adjust value is DVCO
–
ADJUST.
For factory crystal alignment, using standard video signal:
set DVCO = 0, set lock mode, read crystal offset from ADJUST register
and use negative value for initial center frequency adjustment via DVCO.
read only
adjust
h
’
f7
crystal oscillator line-locked mode, lock command/status
write: 100
enable lock
0
disable lock
read: 0
unlocked
>2047
locked
0
xlck
FP Status Register
h
’
12
general purpose control bits
bit[2:0]
bit[3]
bit[8:4]
bit[9]
bit[11:10]
reserved, do not change
vertical standard force
reserved, do not change
disable flywheel interlace
reserved, do not change
to enable vertical free run mode set vfrc to 1 and dflw to 0
0
1
vfrc
dflw
h
’
13
standard recognition status
bit[0]
1
bit[1]
1
bit[2]
1
bit[3]
1
bit[4]
1
bit[5]
1
bit[6]
1
bit[7]
1
bit[8]
1
bit[9]
1
bit[11:10]
vertical lock
horizontally locked
no signal detected
color amplitude killer active
disable amplitude killer
color ident killer active
disable ident killer
interlace detected
no vertical sync detection
spurious vertical sync detection
reserved
–
asr
h
’
cb
number of lines per field, P/S: 312, N: 262
read only
nlpf
h
’
15
vertical field counter, incremented per field
vcnt
h
’
74
measured sync amplitude value, nominal: 768 (PAL), 732 (NTSC)
read only
sampl
h
’
31
measured burst amplitude
read only
bampl
h
’
f0
firmware version number
bit[7:0]
bit[11:8]
internal revision number
firmware release
read only
sw_version
h
’
f1
hardware version number
bit[7:0]
bit[11:8]
internal hardware revision number
hardware id
0000 = VDP 3120B
1000 = VDP 3116B
0100 = VDP 3112B
1100 = VDP 3108B
1110 = VDP 3104B
read only
hw_version