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參數(shù)資料
| 型號： | VDP3108PR |
| 英文描述： | Consumer IC |
| 中文描述： | 消費性IC |
| 文件頁數(shù)： | 23/72頁 |
| 文件大?。?/td> | 597K |
| 代理商： | VDP3108PR |
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PRELIMINARY DATA SHEET
VDP 31xxB
23
Micronas
2.9.3. Average Beam Current Limiter
The average beam current limiter (BCL) uses the sense
input for the beam current measurement. The BCL uses
a different filter to average the beam current during the
active picture. The filter bandwidth is approx. 2 kHz. The
beam current limiter has an automatic offset adjustment
that is active two lines before the first cutoff measure-
ment line.
The beam current limiter function is located in the front-
end. The data exchange between the front-end and the
back-end is done via a single-wire serial interface.
The beam current limiter allows the setting of a threshold
current. If the beam current is above the threshold, the
excess current is low-pass filtered and used to attenuate
the RGB outputs by adjusting the white-drive multipliers
for the internal (digital) RGB signals, and the analog con-
trast multipliers for the analog RGB inputs, respectively.
The lower limit of the attenuator is programmable, thus
a minimum contrast can always be set. During the tube
measurement, the ABL attenuation is switched off. After
the white drive measurement line it takes 3 lines to
switch back to BCL limited drives and brightness.
Typical characteristics of the ABL for different loop gains
are shown in Fig. 2
–
24; for this example the tube has
been assumed to have square law characteristics.
Fig. 2
–
24:
Beam current limiter characteristics:
beam current output vs. drive
BCL threshold: 1
b
drive
2.9.4. Analog RGB Insertion
The VDP 31xxB allows insertion of 2 external analog
RGB signals. Each RGB signal is key-clamped and in-
serted into the main RGB by the fast blank switch. The
selected external RGB input is virtually handled as a
priority bus signal. Thus, it can be overlaid or underlaid
to the digital picture. The external RGB signals can be
adjusted independently as regards DC-level (bright-
ness) and magnitude (contrast).
Which analog RGB input is selected depends on the fast
blank input signals and the programming of a number of
I
2
C-bus register settings (see Table 2
–
3 and Fig. 2
–
25).
Both fast blank inputs must be either active-low or ac-
tive-high.
All signals for analog RGB insertion (RIN1/2, GIN1/2,
BIN1/2, FBLIN1/2, HCS) must be synchronized to the
horizontal flyback, otherwise a horizontal jitter will be vis-
ible. The VDP 31xxB has no means for timing correction
of the analog RGB input signals.
Table 2
–
3:
RGB Input Selection
FBFOH1 = 0, FBFOH2 = 0, FBFOL1 = 0, FBFOL2 = 0
FBLIN1
FBLIN2
FBPOL
FBPRIO
RGB output
0
0
0
x
Video
0
1
0
x
RGB input 2
1
0
0
x
RGB input 1
1
1
0
0
RGB input 1
1
1
0
1
RGB input 2
0
0
1
0
RGB input 1
0
0
1
1
RGB input 2
0
1
1
x
RGB input 1
1
0
1
x
RGB input 2
1
1
1
x
Video
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