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參數(shù)資料
| 型號： | V53C8258L |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | Ultra-High Speed,3.3 Volt 256K x 8 Bit EDO Page Mode CMOS Dynamic RAM(3.3V超高速256Kx8EDO頁面模式CMOS動態(tài)RAM) |
| 中文描述： | 超高速，3.3伏特256K × 8位EDO公司頁面模式的CMOS動態(tài)RAM（3.3超高速256Kx8EDO頁面模式的CMOS動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 144K |
| 代理商： | V53C8258L |
15
V53C8258L Rev. 1.4 February 1999
MOSEL V ITELIC
V53C8258L
Refresh Cycle
To retain data, 512 Refresh Cycles are required
in each 8 ms period. There are two ways to refresh
the memory:
1. By clocking each of the 512 row addresses (A
0
through A
8
) with RAS at least once every 8 ms.
Any Read, Write, Read-Modify-Write or RAS-
only cycle refreshes the addressed row.
2. Using a CAS-before-RAS Refresh Cycle. If CAS
makes a transition from low to high to low after
the previous cycle and before RAS falls, CAS-
before-RAS refresh is activated. The
V53C8258H uses the output of an internal 9-bit
counter as the source of row addresses and
ignore external address inputs.
CAS-before-RAS is a “refresh-only” mode and no
data access or device selection is allowed. Thus,
the output remains in the High-Z state during the
cycle. A CAS-before-RAS counter test mode is
provided to ensure reliable operation of the internal
refresh counter.
Power-On
After application of the V
CC
supply, an initial
pause of 200
m
s is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the V
CC
current requirement
of the V53C8258L is dependent on the input levels
of RAS and CAS. If RAS is low during Power-On,
the device will go into an active cycle and I
CC
will
exhibit current transients. It is recommended that
RAS and CAS track with V
CC
or be held at a valid
V
IH
during Power-On to avoid current surges.
Table 1. V53C8258L Data Output
Operation for Various Cycle Types
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write Cycle
(Early Write)
High-Z
WE-Controlled Write Cycle
(Late Write)
OE Controlled.
High OE = High-Z I/Os
Read-Modify-Write Cycles
Data from Addressed
Memory Cell
EDO Page Mode Read
Data from Addressed
Memory Cell
EDO Page Mode Write Cycle
(Early Write)
High-Z
EDO Page Mode Read-Modify-
Write Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS Refresh Cycle
Data remains as in
previous cycle
CAS-only Cycles
High-Z
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