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參數(shù)資料
| 型號： | V53C832L35 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 3.3 VOLT 256K X 32 EDO PAGE MODE CMOS DYNAMIC RAM |
| 中文描述： | 高性能3.3伏256 × 32 EDO公司頁面模式的CMOS動(dòng)態(tài)隨機(jī)存儲器 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 178K |
| 代理商： | V53C832L35 |
MOSEL VITELIC
1
V53C832L
HIGH PERFORMANCE
3.3 VOLT 256K X 32 EDO PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
V53C832L Rev. 1.6 August 1999
HIGH PERFORMANCE
30
35
40
Max. RAS Access Time, (t
RAC
)
30 ns
35 ns
40 ns
Max. Column Address Access Time, (t
CAA
)
16 ns
18 ns
20 ns
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
12 ns
14 ns
15 ns
Min. Read/Write Cycle Time, (t
RC
)
65 ns
70 ns
75 ns
Features
I
256K x 32-bit organization
I
EDO Page Mode for a sustained data rate of
83 MHz
I
RAS access time: 30, 35, 40 ns
I
Four CAS Inputs for Byte Read and Byte Write
Control
I
Low power dissipation
I
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
I
Refresh Interval: 512 cycles/8 ms
I
Available in 100-pin PQFP and 100-pin LQFP
packages
I
Single +3.3V
±
0.3V Power Supply
I
TTL Interface
Description
The V53C832L is a high speed 262,144 x 32 bit
high performance CMOS dynamic random access
memory. The V53C832L offers a combination of
unique features including: EDO Page Mode opera-
tion for higher sustained bandwidth with Page Mode
cycle times as short as 12ns. All inputs are TTL
compatible. Input and output capacitance is signifi-
cantly lowered to increase performance and mini-
mize loading. These features make the V53C832L
ideally suited for a wide variety of high performance
computer systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
Q
TQ
30
35
40
Std.
0
°
C to 70
°
C
Blank
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