參數(shù)資料
型號: V53C8258L
廠商: Mosel Vitelic, Corp.
英文描述: Ultra-High Speed,3.3 Volt 256K x 8 Bit EDO Page Mode CMOS Dynamic RAM(3.3V超高速256Kx8EDO頁面模式CMOS動態(tài)RAM)
中文描述: 超高速,3.3伏特256K × 8位EDO公司頁面模式的CMOS動態(tài)RAM(3.3超高速256Kx8EDO頁面模式的CMOS動態(tài)內(nèi)存)
文件頁數(shù): 1/18頁
文件大?。?/td> 144K
代理商: V53C8258L
MOSEL V ITELIC
1
V53C8258L
ULTRA-HIGH SPEED,
3.3 VOLT 256K x 8 BIT EDO PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
V53C8258L Rev. 1.4 February 1999
HIGH PERFORMANCE
60
Max. RAS Access Time, (t
RAC
)
60 ns
Max. Column Address Access Time, (t
CAA
)
30 ns
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
27 ns
Min. Read/Write Cycle Time, (t
RC
)
120 ns
Features
I
256K x 8-bit organization
I
Page Mode with Extended Data Output for a
sustained data rate of 37 MHz
I
RAS access time: 60 ns
I
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
I
Refresh Interval: 512 cycles/8 ms
I
Available in 24 pin 300 mil Plastic DIP,
26/24 pin 300 mil SOJ, and 28-pin TSOP-I
packages
I
Single +3.3 V
±
0.3 V power supply
I
TTL Interface
Description
The V53C8258L is a ultra high speed 262,144 x
8 bit CMOS dynamic random access memory. The
V53C8258L offers a combination of features: Page
Mode with Extended Data Output for high data
bandwidth, and Low CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered
to allow increased system performance. Page
Mode with Extended Data Output operation allows
random access of up to 512 (x8) bits within a row
with cycle times as fast as 27 ns. Because of static
circuitry, the CAS clock is not in the critical timing
path. The flow-through column address latches
allow address pipelining while relaxing many critical
system timing requirements. The V53C8258L is
ideally suited for graphics, digital signal processing
and high-performance computing systems.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
P
K
T
60
Std.
0
°
C to 70
°
C
Blank
-40
°
C to 85
°
C
I
-55
°
C to 125
°
C
Ex
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