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參數(shù)資料
| 型號(hào)： | V53C8258L |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | Ultra-High Speed,3.3 Volt 256K x 8 Bit EDO Page Mode CMOS Dynamic RAM(3.3V超高速256Kx8EDO頁面模式CMOS動(dòng)態(tài)RAM) |
| 中文描述： | 超高速，3.3伏特256K × 8位EDO公司頁面模式的CMOS動(dòng)態(tài)RAM（3.3超高速256Kx8EDO頁面模式的CMOS動(dòng)態(tài)內(nèi)存） |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 144K |
| 代理商： | V53C8258L |
14
V53C8258L Rev. 1.4 February 1999
MOSEL V ITELIC
V53C8258L
Functional Description
The V53C8258L is a CMOS dynamic RAM
optimized for high data bandwidth, low power
applications. It is functionally similar to a traditional
dynamic RAM. The V53C8258L reads and writes
data by multiplexing an 18-bit address into a 9-bit
row and a 9-bit column address. The row address is
latched by the Row Address Strobe (RAS). The
column address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be
ended or aborted before the minimum t
RAS
time
has expired. This ensures proper device operation
and data integrity. A new cycle must not be initiated
until the minimum precharge time t
RP
/t
CP
has
elapsed.
Read Cycle
A Read cycle is performed by holding the Write
Enable (WB/WE) signal High during a RAS/CAS
operation. The column address must be held for a
minimum specified by t
AR
. Data Out becomes valid
only when t
OAC
, t
RAC
, t
CAA
and t
CAC
are all
satisifed. As a result, the access time is dependent
on the timing relationships between these
parameters. For example, the access time is limited
by t
CAA
when t
RAC
, t
CAC
and t
OAC
are all satisfied.
Write Cycle
A Write Cycle is performed by taking WB/WE and
CAS low during a RAS operation. The column
address is latched by CAS. The Write Cycle can be
WB/WE controlled or CAS controlled depending on
whether WB/WE or CAS falls later. Consequently,
the input data must be valid at or before the falling
edge of WB/WE or CAS, whichever occurs last. In
the CAS-controlled Write Cycle, when the leading
edge of WE occurs prior to the CAS low transition,
the I/O data pins will be in the High-Z state at the
beginning of the Write function. Ending the Write
with RAS or CAS will maintain the output in the
High-Z state.
In the WB/WE controlled Write Cycle, OE must
be in the high state and t
OED
must be satisfied.
V53C8258L also offers a write-per-bit function.
When WB/WE is “l(fā)ow” at the falling edge of RAS.
The Write-per-bit function is enabled. The mask
data on I/O pins is latched into the write mask
register. Data is written into the DRAM on data lines
where the Write-Mask data is a logic “1”. Writing is
inhibited on data lines where the Write-Mask data
in logic “0”. The Write-Mask data is valid for only
one cycle.
Extended Data Output Page Mode
The V53C8258L offers fast access within a row.
Unlike ordinary fast page mode DRAM, the
V53C8258L output remains active and valid even
after CAS goes high and it will stay valid for 5 ns
after CAS changes low. This feature allows the
V53C8258L to CAS cycle faster than ordinary page
mode DRAM since the cycle time can be short as
data access time.
The outputs are disabled at the t
HZ
time after
RAS and CAS are high. The t
HZ
time is referenced
from rising edge of RAS or CAS whichever occurs
last. In addition, high on OE input and activation of
the write-cycle will also disable the outputs.
The following equation can be used to calculate
the maximum data rate:
Data Output Operation
The V53C8258L Input/Output is controlled by
OE, CAS, WE and RAS. A RAS low transition
enables the transfer of data to and from the
selected row address in the Memory Array. A RAS
high transition disables data transfer and latches
the output data if the output is enabled. After a
memory cycle is initiated with a RAS low transition,
a CAS low transition enables the internal I/O path.
A CAS high transition or RAS high transition,
whichever occurs later, disables the I/O path and
the output driver if it is enabled. A CAS low
transition while RAS is high has no effect on the I/O
data path or on the output drivers. The output
drivers, when otherwise enabled, can be disabled
by holding OE high. The OE signal has no effect on
any data stored in the output latches. A WE low
level can also disable the output drivers. During a
Write cycle, if WE goes low at a time when the CAS
is low, it is necessary to use OE to disable the
output drivers prior to the WE low transition to allow
Data In Setup Time (t
DS
) to be satisfied.
Data Rate
512
511
t
RC
t
PC
′
+
----------------------------------------
=
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