μPD78F921x ONLY) User’s Manual U16994EJ6V0UD 166 9.4 A/D Converter Operations" />
參數(shù)資料
型號(hào)： UPD78F9212CS-CAB-A
廠商： Renesas Electronics America
文件頁數(shù)： 77/175頁
文件大?。?/td> 0K
描述： MCU 8BIT 4KB FLASH 16PIN
標(biāo)準(zhǔn)包裝： 400
系列： 78K0S/Kx1+
核心處理器： 78K0S
芯體尺寸： 8-位
速度： 10MHz
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 13
程序存儲(chǔ)器容量： 4KB（4K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 16-DIP（0.300"，7.62mm）
包裝： 托盤
CHAPTER 9 A/D CONVERTER (
μPD78F921x ONLY)
User’s Manual U16994EJ6V0UD
166
9.4
A/D Converter Operations
9.4.1
Basic operations of A/D converter
<1>
Select one channel for A/D conversion using the analog input channel specification register (ADS).
<2>
Set ADCE to 1 and wait for 1
μs or longer.
<3>
Execute two NOP instructions or an instruction equivalent to two machine cycles.
<4>
Set ADCS to 1 and start the conversion operation.
(<5> to <11> are operations performed by hardware.)
<5>
The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<6>
When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
input analog voltage is held until the A/D conversion operation has ended.
<7>
Bit 9 of the successive approximation register (SAR) is set. The D/A converter voltage tap is set to (1/2) VDD
by the tap selector.
<8>
The voltage difference between the D/A converter voltage tap and analog input is compared by the voltage
comparator. If the analog input is greater than (1/2) AVDD, the MSB of SAR remains set to 1. If the analog
input is smaller than (1/2) VDD, the MSB is reset to 0.
<9>
Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The D/A
converter voltage tap is selected according to the preset value of bit 9, as described below.
Bit 9 = 1: (3/4) VDD
Bit 9 = 0: (1/4) VDD
The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows.
Analog input voltage ≥ Voltage tap: Bit 8 = 1
Analog input voltage < Voltage tap: Bit 8 = 0
<10> Comparison is continued in this way up to bit 0 of SAR.
<11> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result
value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
<12> Repeat steps <5> to <11>, until ADCS is cleared to 0.
To stop the A/D converter, clear ADCS to 0.
To restart A/D conversion from the status of ADCE = 1, start from <3>. To restart A/D conversion from the
status of ADCE = 0, start from <2>.
Cautions 1.
Make sure the period of <1> to <4> is 1
μs or more.
2.
It is no problem if the order of <1> and <2> is reversed.
Remark
The following two types of A/D conversion result registers can be used.
ADCR (16 bits): Stores a 10-bit A/D conversion value.
ADCRH (8 bits): Stores an 8-bit A/D conversion value.
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