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    參數(shù)資料
    型號(hào): UPD78F9212CS-CAB-A
    廠商: Renesas Electronics America
    文件頁數(shù): 61/175頁
    文件大?。?/td> 0K
    描述: MCU 8BIT 4KB FLASH 16PIN
    標(biāo)準(zhǔn)包裝: 400
    系列: 78K0S/Kx1+
    核心處理器: 78K0S
    芯體尺寸: 8-位
    速度: 10MHz
    外圍設(shè)備: LVD,POR,PWM,WDT
    輸入/輸出數(shù): 13
    程序存儲(chǔ)器容量: 4KB(4K x 8)
    程序存儲(chǔ)器類型: 閃存
    RAM 容量: 128 x 8
    電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 16-DIP(0.300",7.62mm)
    包裝: 托盤
    CHAPTER 8 WATCHDOG TIMER
    User’s Manual U16994EJ6V0UD
    151
    8.4
    Operation of Watchdog Timer
    8.4.1
    Watchdog timer operation when “l(fā)ow-speed internal oscillator cannot be stopped” is selected by
    option byte
    The operation clock of watchdog timer is fixed to low-speed internal oscillation clock.
    After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
    the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.
    The following shows the watchdog timer operation after reset release.
    1.
    The status after reset release is as follows.
    Operation clock: Low-speed internal oscillation clock
    Cycle: 218/fRL (546.13 ms: At operation with fRL = 480 kHz (MAX.))
    Counting starts
    2.
    The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
    instruction
    Notes 1, 2.
    Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
    3.
    After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
    Notes 1.
    The operation clock (low-speed internal oscillation clock) cannot be changed. If any value is written to
    bits 3 and 4 (WDCS3, WDCS4) of WDTM, it is ignored.
    2.
    As soon as WDTM is written, the counter of the watchdog timer is cleared.
    Caution
    In this mode, operation of the watchdog timer cannot be stopped even during STOP instruction
    execution. For 8-bit timer H1 (TMH1), a division of the low-speed internal oscillation clock can be
    selected as the count source, so clear the watchdog timer using the interrupt request of TMH1
    before the watchdog timer overflows after STOP instruction execution. If this processing is not
    performed, an internal reset signal is generated when the watchdog timer overflows after STOP
    instruction execution.
    A status transition diagram is shown below
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    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    UPD78F9212FH(T)-2A2-A 制造商:Renesas Electronics Corporation 功能描述:
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