(2) When the watchdog timer operation clock is the low-speed internal oscill" />
參數(shù)資料
型號： UPD78F9212CS-CAB-A
廠商： Renesas Electronics America
文件頁數(shù)： 66/175頁
文件大?。?/td> 0K
描述： MCU 8BIT 4KB FLASH 16PIN
標(biāo)準(zhǔn)包裝： 400
系列： 78K0S/Kx1+
核心處理器： 78K0S
芯體尺寸： 8-位
速度： 10MHz
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 13
程序存儲器容量： 4KB（4K x 8）
程序存儲器類型： 閃存
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 16-DIP（0.300"，7.62mm）
包裝： 托盤
CHAPTER 8 WATCHDOG TIMER
User’s Manual U16994EJ6V0UD
156
(2) When the watchdog timer operation clock is the low-speed internal oscillation clock (fRL) when the STOP
instruction is executed
When the STOP instruction is executed, operation of the watchdog timer is stopped.
After STOP mode is
released, operation stops for 34
μs (TYP.) and then counting is started again using the operation clock before the
operation was stopped. At this time, the counter is not cleared to 0 but holds its value.
Figure 8-7. Operation in STOP Mode (WDT Operation Clock: Low-Speed Internal Oscillation Clock)
<1> CPU clock: Crystal/ceramic oscillation clock
Operating
Oscillation stabilization time
Normal operation
Oscillation stabilization time
(set by OSTS register)
Watchdog timer
Operation stopped
Operating
fRL
fCPU
CPU operation
Normal
operation
STOP
Oscillation stopped
Operation
stoppedNote
<2> CPU clock: High-speed internal oscillation clock or external clock input
Operating
Normal operation
Watchdog timer
Operation stopped
Operating
fRL
fCPU
CPU operation
Normal
operation
STOP
Oscillation stopped
Operation
stoppedNote
Note The operation stop time is 17
μs (MIN.), 34 μs (TYP.), and 67 μs (MAX.).
8.4.4
Watchdog timer operation in HALT mode (when “l(fā)ow-speed internal oscillator can be stopped by
software” is selected by option byte)
The watchdog timer stops counting during HALT instruction execution regardless of whether the operation clock of
the watchdog timer is the system clock (fX) or low-speed internal oscillation clock (fRL). After HALT mode is released,
counting is started again using the operation clock before the operation was stopped. At this time, the counter is not
cleared to 0 but holds its value.
Figure 8-8. Operation in HALT Mode
Watchdog timer
Operating
fX or fRL
fCPU
CPU operation
Normal operation
Operating
HALT
Operation stopped
Normal operation
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