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參數(shù)資料
| 型號： | UPD72042B |
| 廠商： | NEC Corp. |
| 英文描述： | LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL |
| 中文描述： | LSI器件間設備BusTM（IEBusTM）協(xié)議控制 |
| 文件頁數(shù)： | 32/92頁 |
| 文件大?。?/td> | 541K |
| 代理商： | UPD72042B |
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μ
PD72042A, 72042B
32
DATA SHEET S13990EJ2V0DS00
Address
Name
High-order 4 bits
Low-order 4 bits
Note
Reference page
0H
0000
CTR
–
–
–
REEN SRST
–
–
STREQ
A
p. 33
1H
0001
CMR
0
LOCK
BUFC
COMC
C
p. 34
1
0
0
0
0
IRS
MFC
DERC
2H
0010
UAR1
Local station address
(low-order 4 bits)
Condition code
B
p. 36
3H
0011
UAR2
Local station address (high-order 8 bits)
B
p. 36
4H
0100
SAR1
Slave address
(low-order 4 bits)
0
0
0
0
D
p. 37
5H
0101
SAR2
Slave address (high-order 8 bits)
D
p. 37
6H
0110
MCR
Broadcast bits
Number of
arbitrations
Control bits
D
p. 38
7H
0111
–
–
–
–
8H
1000
–
–
–
–
EH
1110
TBF
Number of bytes of transmission data, transmission data
F
p. 40
Table 4-1
μ
PD72042A and
μ
PD72042B Registers
(a) Write registers
(b) Read registers
Address
Name
High-order 4 bits
Low-order 4 bits
Note
Reference page
0H
0000
STR
TFL
TEP
RFL
REP
–
A
p. 41
1H
0001
FLG
–
MARQ STRQ SLRE
CEX
RAW
STM
IRQ
A
p. 42
2H
0010
RDR1
Number of bytes of master reception data
A
p. 44
3H
0011
RDR2
Number of bytes of slave reception data or
broadcast reception data
A
p. 44
4H
0100
LOR1
Lock address (low-order 8 bits)
H
p. 45
5H
0101
LOR2
Lock state
Lock address
(high-order 4 bits)
H
p. 45
6H
0110
DAR1
Broadcast address
(low-order 4 bits)
–
E
p. 46
7H
0111
DAR2
Broadcast address (high-order 8 bits)
E
p. 46
8H
1000
RCR
Return codes (MARC, SLRC)
A
p. 47
EH
1110
RBF
Transmitter address, reception data
G
p. 59
Note
Writable and readable periods of the registers of the
μ
PD72042A and
μ
PD72042B
A: Arbitrary
B: After system reset cancellation
C: While CEX of the FLG register (address 0001) is set to 0
D: While MARQ of the FLG register (address 0001) is set to 0
E: After SLRC of the RCR register (address 1000) is set to 1100 (broadcast reception error)
F: While TFL of the STR register (address 0000) is set to 0
G: While REP of the STR register (address 0000) is set to 0
H: When CEX of the FLG register (address 0001) is set to 0 after LOCK of the CMR register (address 0001)
is set to 1
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