參數(shù)資料
型號(hào)： UPD72042B
廠商： NEC Corp.
英文描述： LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL
中文描述： LSI器件間設(shè)備BusTM（IEBusTM）協(xié)議控制
文件頁(yè)數(shù)： 23/92頁(yè)
文件大?。?/td> 541K
代理商： UPD72042B
μ
PD72042A, 72042B
23
DATA SHEET S13990EJ2V0DS00
Table 3-1 I/O States of the SIO (SI) and SO Pins
RESET
CS
SEL
C/D
SI (SIO)
SO
State
Three-wire/two-wire
Operating mode
0
×
×
×
I
Hi-Z
–
Reset state
1
1
×
×
I
Hi-Z
–
Chip nonselected state
1
0
1
1
I
O*
Three-wire
Control mode
0
Data write mode
O
Data read mode
0
1
I
Hi-Z
Two-wire
Control mode
0
Data write mode
O
Data read mode
I
O
O* : State in which 1 is output
: Input state
: Output state
Hi-Z
×
: High-impedance state
: Don’t care
3.2 DATA TRANSFER FORMAT
3.2.1 Three-Wire Data Transfer (SEL = 1)
(1) Control mode
When the C/D input is set high, control mode is set to control data transfer. Data transfer control involves the
following processing.
1
Register address setting
2
Register read/write selection
(a)
μ
PD72042A (starting with MSB)
(b)
μ
PD72042B (starting with LSB)
C/D
SCK
SI
A3 A2 A1 A0
R
/
W
×
×
×
C/D
SCK
SI
A3
A2
A1
A0
R
/
W
×
×
×
Remark
After reset (RESET) cancellation, the state enabling writing to the register at address 0000B is set.
Caution In control mode, each data item is read every eighth clock pulse. (Data of less than eight clock
periods is ignored.)
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