參數(shù)資料
型號(hào)： UPD70741
廠商： NEC Corp.
元件分類： 16位微控制器
英文描述： V821TM 32-/16-BIT MICROPROCESSOR
中文描述： V821TM 32-/16-BIT微處理器
文件頁(yè)數(shù)： 62/112頁(yè)
文件大?。?/td> 605K
代理商： UPD70741
μ
PD70741
62
16. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (T
A
= 25
°
C)
Parameter
Symbol
Conditions
Rating
Unit
Supply voltage
V
DD
-0.5 to +7.0
V
Input voltage
V
I
V
DD
= +5.0 V
±
10 %
-0.5 to V
DD
+ 0.3
V
Clock input voltage
V
K
V
DD
= +5.0 V
±
10 %
-0.5 to V
DD
+ 0.3
V
Output voltage
V
O
V
DD
= +5.0 V
±
10 %
-0.5 to V
DD
+ 0.3
V
Operating ambient temperature
T
A
-40 to +85
°
C
Storage temperature
T
stg
-65 to +150
°
C
Cautions 1. Do not connect an output (or input/output) pin of an IC device directly to any other output (or
input/output) pin of the same device, or directly to V
DD
, V
CC
, or GND. Open-drain pins and
open-collector pins can, however, be connected directly to each other. Note, however, that
these restrictions do not apply to those high-impedance pins that are provided with an external
circuit for which timings have been designed such that no output contention occurs.
2. Absolute maximum ratings are rated values beyond which some physical damages may be
caused to the product; if any of the parameters in the table above exceeds its rated value even
for a moment, the quality of the product may deteriorate. Be sure to use the product with a
moderate value within the rated range.
The standard values and conditions listed in the DC and AC characteristics tables indicate
the ranges in which the normal operation and performance of the product can be guaranteed.
DC CHARACTERISTICS (T
A
= -40 to +85
°
C, V
DD
= +5.0 V
±
10 %)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Low-level clock input voltage
V
KL
-0.5
+0.6
V
High-level clock input voltage
V
KH
4.0
V
DD
+ 0.3
V
Low-level input voltage
V
IL1
Other than RESET, NMI, and INTPn
-0.5
+0.8
V
V
IL2
RESET, NMI, and INTPn
-0.5
+0.2V
DD
V
High-level input voltage
V
IH1
Other than RESET, NMI, and INTPn
2.2
V
DD
+ 0.3
V
V
IH2
RESET, NMI, and INTPn
0.8V
DD
V
DD
+ 0.3
V
Schmitt-triggered input hysteresis width V
SH
RESET, NMI, and INTPn
0.5
V
Low-level output voltage
V
OL
I
OL
= 2.5 mA
0.45
V
High-level output voltage
V
OH
I
OH
= -2.5 mA
0.7V
DD
V
I
OH
= -100
μ
A
V
DD
- 0.4
V
Low-level input leakage current
I
LIL
V
IN
= 0 V
-10
μ
A
High-level input leakage current
I
LIH
V
IN
= V
DD
10
μ
A
Low-level output leakage current
I
LOL
V
O
= 0 V
-10
μ
A
High-level output leakage current
I
LOH
V
O
= V
DD
10
μ
A
Supply current
I
DD
Operation (f = 25 MHz)
100
150
mA
HALT (f = 25 MHz)
18
45
mA
IDLE (f = 25 MHz)
4
35
mA
STOP
5
20
μ
A
相關(guān)PDF資料
PDF描述
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