參數(shù)資料
型號(hào)： UPD70741
廠商： NEC Corp.
元件分類(lèi)： 16位微控制器
英文描述： V821TM 32-/16-BIT MICROPROCESSOR
中文描述： V821TM 32-/16-BIT微處理器
文件頁(yè)數(shù)： 59/112頁(yè)
文件大小： 605K
代理商： UPD70741
μ
PD70741
59
Table 15-1. Instruction Mnemonics (In Alphabetical Order) (7/9)
Instruction
Operand (s)
Format
CY OV
S
Z
Instruction function
mnemonic
RETI
-
II
*
*
*
*
Return from a trap or interrupt routine:
Reads the restore PC and PSW from the system
registers and loads them to the due places to return
from a trap or interrupt routine to the original operation
flow.
SAR
reg1, reg2
I
*
0
*
*
Arithmetic right shift:
Shifts every bit of the word data in the reg2-specified
register to the right by the number of times specified
with the reg1-specified register’s lowest 5 bits, then
stores the result into the reg2-specified register. In
arithmetic right shift operations, the MSB is loaded
with the LSB value at each shift.
SAR
imm5, reg2
II
*
0
*
*
Arithmetic right shift:
Zero-extends the 5-bit immediate data to 32 bits, shifts
every bit of the word data in the reg2-specified register
to the right by the number of times specified with the
extended immediate data, then stores the result into
the reg2-specified register.
SCH0BSU
SCH0BSD
-
-
II
II
-
-
-
-
-
-
*
*
Searching 0s in a bit string:
Searches “0” bits in the source bit string, and loads r30
and r27 with the address of the bit next to the first
detected “0” bit, then r29 with the number of bits
skipped until the first “0” bit is detected, and r28 with
the value subtracted by the r29 value.
SCH1BSU
SCH1BSD
-
-
II
II
-
-
-
-
-
-
-
-
Searching 1s in a bit string:
Searches 1s in the source bit string, and loads r30 and
r27 with the bit address next to the first detected “1”
bit, then r29 with the number of bits skipped until the
first “1” is detected, and r28 with the value subtracted
by the r29 value.
SETF
imm5, reg2
II
-
-
-
-
Flag condition setting:
Sets the reg2-specified register to 1 if the condition
flag value matches the lowest 4 bits of the 5-bit
immediate data, and sets the reg2-specified register
to 0 when they do not match.
SHL
reg1, reg2
I
*
0
*
*
Logical left shift:
Shifts every bit of the word data in the reg2-specified
register to the left by the number of times specified
with the reg1-specified register’s lowest 5 bits, then
stores the result into the reg2-specified register. In
logical left shift operations, the LSB is loaded with 0
at each shift.
相關(guān)PDF資料
PDF描述
UPD70741GC-25-8EU V821TM 32-/16-BIT MICROPROCESSOR
UPD70F3003A V853TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER
UPD70F3003AGC-25-8EU Circular Connector; No. of Contacts:24; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:25-24 RoHS Compliant: No
UPD70F3025AGC-25-8EU V853TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER
UPD70F3003AGC-33-8EU LJT 29C 29#16 PIN PLUG
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD70741GC-25-8EU 制造商:NEC 制造商全稱:NEC 功能描述:V821TM 32-/16-BIT MICROPROCESSOR
UPD70742GD-25-LML 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
UPD70F30025AGC-25 制造商:NEC 制造商全稱:NEC 功能描述:32-bit RISC Microcontrollers
UPD70F30025AGC-33 制造商:NEC 制造商全稱:NEC 功能描述:32-bit RISC Microcontrollers
UPD70F3003A 制造商:NEC 制造商全稱:NEC 功能描述:V853TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER
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