參數(shù)資料
型號: UPD70741
廠商: NEC Corp.
元件分類: 16位微控制器
英文描述: V821TM 32-/16-BIT MICROPROCESSOR
中文描述: V821TM 32-/16-BIT微處理器
文件頁數(shù): 56/112頁
文件大?。?/td> 605K
代理商: UPD70741
μ
PD70741
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Table 15-1. Instruction Mnemonics (In Alphabetical Order) (4/9)
Instruction
Operand (s)
Format
CY OV
S
Z
Instruction function
mnemonic
IN.W
disp16 [reg1], reg2
VI
-
-
-
-
Port input:
Sign-extends the 16-bit displacement to 32 bits, and
adds the extended displacement and the content of
the reg1-specified register to generate a 32-bit unsigned
port address, then reads the word data located at the
generated address while masking the address’s bits
0 and 1 to 0, and stores the word into the reg2-
specified register.
JAL
disp26
IV
-
-
-
-
Jump and link:
Increments the current PC by 4, then saves it into r31,
and sign-extends the 26-bit displacement to 32 bits
while masking the displacement’s bit 0 to 0, adds the
extended displacement and the PC value, loads the
PC with the addition result, so that the instruction
stored at the PC-pointing address is executed next.
JMP
[reg1]
I
-
-
-
-
Register-indirect unconditional branch:
Loads the PC with the jump address value in the reg1-
specified register while masking the value’s bit 0 to 0,
so that the instruction stored at the address pointed
by the reg1-specified register is executed next.
JR
disp26
IV
-
-
-
-
Unconditional branch:
Sign-extends the 26-bit displacement to 32 bits while
masking bit 0 to 0, adds the result with the current PC
value, and loads the PC with the addition result so that
the instruction stored at the PC-pointing address is
executed next.
LD.B
disp16 [reg1], reg2
VI
-
-
-
-
Byte load:
Sign-extends the 16-bit displacement to 32 bits, and
adds the result with the content of the reg1-specified
register to generate the 32-bit unsigned address, then
reads the byte data located at the generated address,
sign-extends the byte data to 32 bits, and stores the
result into the reg2-specified register.
LD.H
disp16 [reg1], reg2
VI
-
-
-
-
Halfword load:
Sign-extends the 16-bit displacement to 32 bits, and
adds the result with the content of the reg1-specified
register to generate a 32-bit unsigned address while
masking its bit 0 to 0, then reads the halfword data
located at the generated address, sign-extends the
halfword data to 32 bits, and stores the result into the
reg2-specified register.
LD.W
disp16 [reg1], reg2
VI
-
-
-
-
Word load:
Sign-extends the 16-bit displacement to 32 bits and
adds the result with the content of the reg1-specified
register to generate a 32-bit unsigned address while
masking bits 0 and 1 to 0, then reads the word data
located at the generated address and stores the data
into the reg2-specified register.
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