參數(shù)資料
型號: UPD70741
廠商: NEC Corp.
元件分類: 16位微控制器
英文描述: V821TM 32-/16-BIT MICROPROCESSOR
中文描述: V821TM 32-/16-BIT微處理器
文件頁數(shù): 55/112頁
文件大?。?/td> 605K
代理商: UPD70741
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PD70741
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Table 15-1. Instruction Mnemonics (In Alphabetical Order) (3/9)
Instruction
Operand (s)
Format
CY OV
S
Z
Instruction function
mnemonic
CVT.SW
reg1, reg2
VII
-
0
*
*
Data conversion from floating-point to integer:
Converts the single-precision floating-point data in the
reg1-specified register into an integer data, then stores
the result into the reg2-specified register while changing
flags according to the result.
CVT.WS
reg1, reg2
VII
*
0
*
*
Data conversion from integer to floating-point:
Converts the integer data in the reg1-specified register
into a single-precision floating-point data, then stores
the result into the reg2-specified register while changing
flags according to the result.
DIV
reg1, reg2
I
-
*
*
*
Signed division:
Divides the word data in the reg2-specified register by
that for reg1 with their sign bits validated, then stores
the quotient into the reg2-specified register and the
remainder into r30. Division is performed so that the
sign of the remainder matches that of the dividend.
DIVF.S
reg1, reg2
VII
*
0
*
*
Floating-point division:
Divides the single-precision floating-point data in the
reg2-specified register by that for reg1, then stores the
result into the reg2-specified register while changing
flags according to the result.
DIVU
reg1, reg2
I
-
0
*
*
Unsigned division:
Divides the word data in the reg2-specified register by
that for reg1 with their data handled as unsigned data,
then stores the quotient into the reg2-specified register
and the remainder into r30. Division is performed so
that the sign of the remainder matches that of the
dividend.
HALT
-
II
-
-
-
-
Processor stop
IN.B
disp16 [reg1], reg2
VI
-
-
-
-
Port input:
Sign-extends the 16-bit displacement to 32 bits, and
adds the extended displacement and the content of
the reg1-specified register to generate a 32-bit unsigned
port address, then reads the byte data located at the
generated port address, zero-extends the byte data to
32 bits, and stores the result into the reg2-specified
register.
IN.H
disp16 [reg1], reg2
VI
-
-
-
-
Port input:
Sign-extends the 16-bit displacement to 32 bits, and
adds the extended displacement and the content of
the reg1-specified register to generate a 32-bit unsigned
port address, then reads the halfword data located at
the generated port address while masking the address’s
bit 0 to 0, zero-extends the halfword data to 32 bits,
and stores the result into the reg2-specified register.
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