參數(shù)資料
型號: UPD70741
廠商: NEC Corp.
元件分類: 16位微控制器
英文描述: V821TM 32-/16-BIT MICROPROCESSOR
中文描述: V821TM 32-/16-BIT微處理器
文件頁數(shù): 60/112頁
文件大小: 605K
代理商: UPD70741
μ
PD70741
60
Table 15-1. Instruction Mnemonics (In Alphabetical Order) (8/9)
Instruction
Operand (s)
Format
CY OV
S
Z
Instruction function
mnemonic
SHL
imm5, reg2
II
*
0
*
*
Logical left shift:
Zero-extends the 5-bit immediate data to 32 bits, shifts
every bit of the word data in the reg2-specified register
to the left by the number of times specified by the
extended immediate data, then stores the result into
the reg2-specified register.
SHR
reg1, reg2
I
*
0
*
*
Logical right shift:
Shifts every bit of the word data in the reg2-specified
register to the right by the number of times specified
with the reg1-specified register’s lowest 5 bits, then
stores the result into the reg2-specified register. In
logical right shift operations, the MSB is loaded with
0 at each shift.
SHR
imm5, reg2
II
*
0
*
*
Logical right shift:
Zero-extends the 5-bit immediate data to 32 bits, shifts
every bit of the word data in the reg2-specified register
to the right by the number of times specified by the
extended immediate data, then stores the result into
the reg2-specified register.
ST.B
reg2, disp16 [reg1]
VI
-
-
-
-
Byte store:
Sign-extends the 16-bit displacement to 32 bits and
adds the 32-bit displacement and the content of the
reg1-specified register to generate a 32-bit unsigned
address, then transfers the reg2-specified register’s
lowest 8 bits to the generated address.
ST.H
reg2, disp16 [reg1]
VI
-
-
-
-
Halfword store:
Sign-extends the 16-bit displacement to 32 bits with
its bit 0 masked to 0, and adds the content of the reg1-
specified register and the 32-bit displacement to generate
a 32-bit unsigned address, then transfers the reg2-
specified register’s lower 16 bits to the generated
address.
ST.W
reg2, disp16 [reg1]
VI
-
-
-
-
Word store:
Sign-extends the 16-bit displacement to 32 bits with
its bits 0 and 1 masked to 0, and adds the reg1-
specified register and the 32-bit displacement to generate
a 32-bit unsigned address, then transfers the word
data of the reg2-specified register to the generated
address.
STSR
regID, reg2
II
-
-
-
-
Storing system register contents:
Loads the reg2-specified register with the content of
the system register specified by the system register
number (regID).
SUB
reg1, reg2
I
*
*
*
*
Subtraction:
Subtracts the word data in the reg1-specified register
from that in the reg2-specified register, then stores the
result into the reg2-specified register.
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