
Data Sheet S15082EJ4V0DS
8
μ
PD61051, 61052
3.2.5 Download interrupt register .......................................................................................................47
3.2.6 Interrupt register........................................................................................................................48
3.2.7 Reset register............................................................................................................................48
3.2.8 ROM access cycle register........................................................................................................49
3.2.9 Port setup register.....................................................................................................................49
4. SYSTEM INTERFACE PROCEDURE.......................................................................................... 50
4.1
Outline..................................................................................................................................................51
4.2
Firmware Download ............................................................................................................................52
4.2.1 Host CPU to instruction RAM of internal CPU...........................................................................52
4.2.2 External ROM to instruction RAM of internal CPU.....................................................................53
4.2.3 Host CPU to SDRAM.................................................................................................................54
4.2.4 External ROM to SDRAM..........................................................................................................55
4.3
SDRAM Write during Executing.........................................................................................................56
4.4
SDRAM Read during Executing .........................................................................................................57
4.5
SDRAM Initialization............................................................................................................................58
4.6
Operation Mode Setting by Changing Firmware ..............................................................................59
4.7
Transfer Ending...................................................................................................................................60
4.8
Transfer Error Handling......................................................................................................................61
4.8.1 Transfer error handling 1...........................................................................................................61
4.8.2 Transfer error handling 2...........................................................................................................62
4.8.3 Transfer error handling 3...........................................................................................................63
5. EXAMPLE FOR COMMON REGISTER USAGE....................................................................... 64
5.1
Register Map Example........................................................................................................................65
5.2
Example of the Common Register Which A Firmware Defines.......................................................67
5.2.1 COMCODE: Command code register........................................................................................66
5.2.2 ESTS: Status register................................................................................................................66
6. ELECTRICAL CHARACTERISTICS............................................................................................. 68
7. PACKAGE DRAWING ................................................................................................................102
8. RECOMMENDED SOLDERING CONDITIONS.........................................................................103