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參數資料
| 型號： | UPD61052GD-LML |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| 中文描述： | 馬鞍山集成電路MPEG2音頻/視頻編碼器 |
| 文件頁數： | 42/106頁 |
| 文件大?。?/td> | 824K |
| 代理商： | UPD61052GD-LML |
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Data Sheet S15082EJ4V0DS
42
μ
PD61051, 61052
(2)
Source address register
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
21H
SA19 to SA16
R/W
Source address
22H
SA15 to SA8
R/W
Source address
23H
SA7 to SA0
R/W
Source address
It sets the address of the data to transfer. It becomes effective in case of transfer from SDRAM or instruction ROM.
Until it releases a transfer mode after setting a transfer mode register, it isn't possible to change. The transfer error
occurs when rewriting this register before releasing a transfer mode. The relation with the address of SDRAM,
external instruction ROM is shown in
Figure 3-2
and
3-3
. The addressing of SDRAM becomes a 32 address by
4-word unit (128 bytes).
The relation with the SDRAM bank and address is shown in
Table 3-1
.
Figure 3-2. Relation of Source Address and SDRAM Address
Host CPU
interface register
21H to 23H
0 0 0 0
0 0 0 0 0
SDRAM address
The μPD61051/61052
adds 0 automatically
S
S
S
S
S
S
S
S
S
S
S
S
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
S
S
S
S
S
S
S
S
Bank select
Figure 3-3. Relation of Source Address and External Instruction ROM Address
0 0 0 0
Extemal
instruction ROM
address
Host CPU
interface register
21H to 23H
S
S
S
S
S
S
S
S
S
S
S
S
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
S
S
S
S
S
S
S
S
Table 3-1. Relation of SDRAM Bank and Address
Memory
Bank A
Bank B
Bank C
Bank D
16 Mbit SDRAM by 2
000000H to 07FFFFH
200000H to 27FFFFH
-
-
16 Mbit SDRAM by 1
000000H to 07FFFFH
200000H to 27FFFFH
100000H to 17FFFFH
300000H to 37FFFFH
64 Mbit SDRAM by 2
128 Mbit SDRAM by 1
128 Mbit SDRAM by 2
000000H to 0FFFFFH
200000H to 2FFFFFH
100000H to 1FFFFFH
300000H to 3FFFFFH
128 Mbit SDRAM by 1
000000H to 0FFFFFH
200000H to 2FFFFFH
100000H to 1FFFFFH
300000H to 3FFFFFH
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