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參數(shù)資料
| 型號： | UPD61052GD-LML |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| 中文描述： | 馬鞍山集成電路MPEG2音頻/視頻編碼器 |
| 文件頁數(shù)： | 55/106頁 |
| 文件大小： | 824K |
| 代理商： | UPD61052GD-LML |
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Data Sheet S15082EJ4V0DS
55
μ
PD61051, 61052
4.2.4
External ROM to SDRAM
The firmware for the internal CPU can be stored in the firmware cabinet of SDRAM from the external ROM. It
stores more than one piece of firmware beforehand and it can be replaced according to need, too.
When transferring data continuously, transfer during resetting an internal CPU, If reset of internal CPU is can
canceled on the way, the internal CPU sometime malfunction. When transferring data below the 1k-byte, transfer,
dividing every 128 bytes. The number of the transfer bytes is a 4-byte unit.
(a) Transfer over 1 Kbytes
(b) Transfer below 128 bytes
Instruction
download
(Serial bus)
Destination address register
(24H to 26H) setting
Source address register
(21H to 23H) setting
Internal CPU reset
Reset register (3EH)
←
02H setting
Number of transfer bytes /4
Transfer counter register
(27H to 29H) setting
After 70
μ
sec
Clear mask transfer interrupt
Interrupt mask0 (2BH)
←
00H
iROM
→
SDRAM transfer
Transfer mode register
(20H)
←
10H setting
Interrupt mask0 (2BH)
←
0
3H setting
Transfer ending
(refer to
4.7
)
Return
Internal CPU reset is canceled
Reset register
(3EH)
←
00H setting
Instruction
download
(Serial bus)
Destination address register
(24H to 26H) setting
Source address register
(21H to 23H) setting
Internal CPU reset
Reset register (3EH)
←
02H setting
Number of transfer bytes /4
Transfer counter register
(27H to 29H) setting
iROM
→
SDRAM transfer
Transfer mode register
(20H)
←
10H setting
Transfer ending
(refer to
4.7
)
Return
Internal CPU reset is canceled
Reset register
(3EH)
←
00H setting
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