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參數資料
| 型號： | UPD61052GD-LML |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| 中文描述： | 馬鞍山集成電路MPEG2音頻/視頻編碼器 |
| 文件頁數： | 47/106頁 |
| 文件大?。?/td> | 824K |
| 代理商： | UPD61052GD-LML |
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Data Sheet S15082EJ4V0DS
47
μ
PD61051, 61052
3.2.3
Internal CPU interrupt register
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
2AH
iCPU-INT
R/W
Int. to internal CPU
Host CPU set interrupt to internal CPU. Internal CPU clears this bit after interrupt operation.
The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H.
3.2.4
Interrupt mask register
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
2BH
DMA-ERR
-M
DMA-RDY
-M
DMA-DON
E-M
R/W
Interrupt mask0
2CH
Defined by firmware
R/W
Interrupt mask1
2DH
Defined by firmware
R/W
Interrupt mask2
2EH
Defined by firmware
R/W
Interrupt mask3
2FH
Defined by firmware
R/W
Interrupt mask4
These registers are interrupt masks for next interrupt. Interrupt mask can be set bit by bit. When setting an
interrupt mask, CINT does not become high even if the interrupt register becomes 1.
The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H.
3.2.5
Download interrupt register
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
30H
DMA-ERR
DMA-RDY
DMA-DON
E
R/W
Interrupt0
It is set for 1 when the interrupt factor occurs.
The interrupt bit clears when host CPU writes to this register after the interrupt processing.
The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H.
Clear processing continues until interrupt registers is cleared.
Bit
Field
Function
Initial value
7 to 3
Reserved (set 0)
2
DMA-ERR
Data transfer error
0: Normal, 1: Error
0
1
DMA-RDY
Data transfer prepared
0: Normal, 1: Transfer
0
0
DMA-DONE
Data transfer ended
0: Normal, 1: Transfer ended
0
It outputs DMA-RDY or DMA-DONE every 128-byte transfer. DMA-DONE is output when the transfer ends.
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