參數(shù)資料
型號(hào)： UPD61052GD-LML
廠商： NEC Corp.
英文描述： MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER
中文描述： 馬鞍山集成電路MPEG2音頻/視頻編碼器
文件頁(yè)數(shù)： 45/106頁(yè)
文件大?。?/td> 824K
代理商： UPD61052GD-LML
Data Sheet S15082EJ4V0DS
45
μ
PD61051, 61052
SDRAM read
<1> Interrupt mask
Host CPU sets mask bit to interrupt mask register (2CH to 2FH) for the interrupt that needs a data transfer.
<2> Set source address
Host CPU sets the address of SDRAM to the source address register (21H to 23H) of the
μ
PD61051/61052.
<3> Set the number (equal to or less than 128 bytes) of the data to read by 4 bytes unit
Host CPU sets the data number of the bytes to the transfer data counter register (27H to 29H) of the
μ
PD61051/61052.
<4> Set the transfer of SDRAM
→
host CPU.
Host CPU sets 01H to the transfer mode register (20H) of the
μ
PD61051/61052.
<5> CINT interrupt (Interrupt pin)
<6> Confirms that the interrupt factor and clear interrupt factor
Host CPU confirms that the interrupt register 0 (30H) of the
μ
PD61051/61052 becomes 02H or 01H and clears
writing a same value of the interrupt register 0 (30H) to the interrupt register 0 (30H) of the
μ
PD61051/61052.
<7> Data read
Host CPU reads data from the number of times with the set number of bytes, the transfer data register (3FH) of
the
μ
PD61051/61052.
<8> CINT interrupt (Interrupt pin)
<9> Confirm the interrupt factor
Host CPU confirms that the interrupt register 0 (30H) of the
μ
PD61051/61052 becomes 01H. (It clears a writing
interrupt factor in 01H at the interrupt register 0 (30H) register of the
μ
PD61051/61052.)
<10> Release of SDRAM
→
host CPU mode
Host CPU clears a writing interrupt factor in 01H at the interrupt register 0 (30H) register of the
μ
PD61051/61052
after setting 00H to the transfer mode register (20H) of the
μ
PD61051/61052.
<11> Release of interrupt mask
It releases the limitation on interrupt which set by <1>.
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