參數(shù)資料
型號(hào): UPD17201AGF
廠商: NEC Corp.
英文描述: 4-BIT SINGLE-CHIP MICROCONTROLLER WITH LCD CONTROLLER/DRIVER AND A/D CONVERTER FOR INFRARED REMOTE CONTROL TRANSMITTERS
中文描述: 4位單片機(jī)與LCD控制器/驅(qū)動(dòng)器和A / D轉(zhuǎn)換器紅外遙控遞質(zhì)
文件頁(yè)數(shù): 83/120頁(yè)
文件大?。?/td> 516K
代理商: UPD17201AGF
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μ
PD17201A, 17207
83
14. RESET
14.1
RESET BY RESET SIGNAL INPUT
When a low-level signal is input to the RESET pin for 50
μ
s or more, the system is reset.
The system must be reset at least once when the power is turned on, as the operation of the internal circuit is
undefined.
When reset has been effected, the following circuits are initialized:
1
2
3
4
5
The program counter is reset to 0.
The flags of the register file are initialized (for the initial values, refer to Fig. 15-1 Register File List).
Initial value 0320H is written to the data buffer.
The peripheral hardware is initialized.
Oscillation of the main clock is stopped.
When the RESET pin is made high, oscillation of the main clock is started, and about 64 ms after that (where the
main clock frequency is 4 MHz), execution of the program is started from address 0.
Fig. 14-1 Reset Operation by RESET Input
14.2
RESET BY WATCHDOG TIMER (RESET AND WDOUT PINS CONNECTED)
When the watchdog timer is activated while the program is being executed, a low level is output to the WDOUT
pin, and the program counter is reset to 0.
Therefore, when the watchdog timer is not reset for a fixed period of time, the program can be restarted from address
0.
When developing a program, reset the watchdog timer (set the WDTRES flag) at intervals of 340 ms or less (where
f
x
= 4 MHz).
14.3
RESET BY STACK POINTER (RESET AND WDOUT PINS CONNECTED)
When the value of the stack pointer reaches 6H or 7H while the program is being executed, a low level is output
to the WDOUT pin, and the program counter is reset to 0.
When the level of nesting of interrupt or subroutine call exceeds 5 (stack overflow), or when the return instruction
is executed despite the stack level being 0 because the call instruction and return (RET) instruction have not been
correctly used in pairs (stack underflow), the program can be restarted from address 0.
Wait
(approx. 64 ms/4 MHz)
Starts from address 0
RESET
Operation mode or
standby mode
Main clock oscillation stopped
HALT mode
Operation mode
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