參數(shù)資料
型號: UPD17201AGF
廠商: NEC Corp.
英文描述: 4-BIT SINGLE-CHIP MICROCONTROLLER WITH LCD CONTROLLER/DRIVER AND A/D CONVERTER FOR INFRARED REMOTE CONTROL TRANSMITTERS
中文描述: 4位單片機(jī)與LCD控制器/驅(qū)動器和A / D轉(zhuǎn)換器紅外遙控遞質(zhì)
文件頁數(shù): 52/120頁
文件大?。?/td> 516K
代理商: UPD17201AGF
μ
PD17201A, 17207
52
9.5 OPERATION IN COMPARE MODE
In the compare mode, the result of comparison stored to ADCCMP is read and then the next comparison is
immediately performed. Therefore, comparison is executed successively and the ADCCMP flag is rewritten
accordingly.
The timing necessary for compare mode differs depending on whether the main clock or subclock is selected as
the system clock.
(1) When main clock is selected as system clock
The following wait times must be set in software in the compare mode.
Wait time <1>: Time of transition from operation stop mode to compare mode (10 instruction cycles)
Wait time <2>: Wait time until compare result register can be read (first time only) (3 instruction cycles)
Wait time <3>: Wait time until compare result register can be read (second time and onward) (7 instruction
cycles)
Sets compare mode or changes pin
(VREFEN, ADCEN, ADCCH1, ADCCH0)
(Set + compare)
Wait time < 1 > + wait time < 2 >
(13 instruction cycles)
(Compare)
Wait time < 3 > (7 instruction cycles)
(Compare)
Wait time < 3 > (7 instruction cycles)
(Compare)
Wait time < 3 > (7 instruction cycles)
Reads ADCCMP
Reads ADCCMP
Reads ADCCMP
An example of a program in the compare mode when the main clock is selected is shown below.
COMPARE:
INITFLG
NOT VREFEN,NOT ADCEN,ADCCH1,ADCCH0
; Starts comparing voltages of ADC
3
and ADC
1
REPT
NOP
ENDR
PEEK
REPT
NOP
ENDR
PEEK
13
WR,.MF.ADCCMP SHR 4 AND 0FFFH
7
; Reads result of comparison
WR,.MF.ADCCMP SHR 4 AND 0FFFH
; Reads result of comparison
Waits for duration of 13 instruction cycles
or more until comparison ends
Waits for duration of 7 instruction cycles
or more until comparison ends
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