
μ
PD17201A, 17207
54
10. SERIAL INTERFACE
Serial interface consists of an 8-bit shift register, a 4-bit shift mode register, and a 3-bit counter, and transmits data
in series to and from the bus.
10.1
SERIAL INTERFACE FUNCTION
10.1.1
8-bit Data Transfer in Synchronization with Clocks (Simultaneous transmission and reception)
Input and output of serial data on serial interface is controlled by the serial clock (SCK) signal. At the falling edge
of the SCK signal, the most significant bit of the shift register is output from the SO pin (pin 59; also used as P1A
1
).
At the rising edge of the SCK signal, the contents of the shift register are shifted left by one bit and, at the same time,
data input via the SI pin (pin 60; also used as P1A
2
) is set in the least significant bit of the shift register.
The 3-bit counter counts serial clock pulses. Each time the counter counts eight clock pulses (each time serial
data of 8 bits is transferred), the IRQSIO flag (bit 3, address 3BH) of the register file is turned on (“1”) to make an
interrupt request.
10.1.2
8-bit Data Reception in Synchronism with Clocks (High-impedance SO output)
This operation is basically the same as the above operation except that the SI pin (pin 59; also used as P1A
1
) goes
into a high-impedance state and does not output serial data. Therefore, the SO pin can be used as a port (P1A
1
).
10.2
SERIAL INTERFACE OPERATION
10.2.1
Serial Interface Operation Modes
P1A
2
/SI (pin 60), P1A
1
/SO (pin 59), and P1A
0
/SCK (pin 58) are placed in Serial Interface mode when the SIOEN
flag (bit 0, address 23H) of the register file is turned on (“1”). These pins can be used as port pins when the SIOEN
flag is off (“0”). As this operation mode disables transfer of serial data, the shift register can be used as an 8-bit register.
10.2.2
Serial Operation Mode
The serial operation mode is determined by the status of the SIOHIZ flag (bit 2, address 22H) of the register file.
When this flag is off (“0”), a clock-synchronous 8-bit transmission/reception mode is set. When this flag is on (“1”),
a clock-synchronous 8-bit reception mode is set. Figure 10-1 shows shift timing waveforms. The only difference
between these two modes is whether the SO pin (pin 59; also used as P1A
1
) goes into a high-impedance state.
In transmission of serial data, data to be transmitted is set in the shift register SIOSFR (peripheral address 01H)
via the data buffer (DBF) by an PUT instruction, and the SIOTS flag (bit3, address 22H) of the register file is turned
on (“1”). Thus serial data trasfer starts. When 8 bits of data are transferred, the SIOTS flag is automatically turned
off (“0”) and the IRQSIO flag (bit 3, address 3BH) of the register file is turned on (“1”) to generate an interrupt. If
generation of an interrupt is disabled, the end of transfer can be indicated by the SIOTS and IRQSIO flags.
Reception of serial data is basically the same as the transmission of serial data except that data is output from
the SO pin.
The
μ
PD17207 supports four kinds of clock signals (three internal clocks and one external clock) to be selected
as the serial clock source. These clock signals are selected by SIOCK1 (bit 1, address 22H) and SIOCK0 (bit 0,
address 22H) of the register file.
If one of the three internal clock signals is selected as the serial clock source, it is supplied to serial interface when
the SIOTS flag turns on (“1”). The clock controls input/output of serial data and is output from the SCK pin (pin 58;
also used as P1A0). When eight clock pulses are supplied to the serial interface, the SIOTS flag is automatically turned
off (“0”) and the supply of clock pulses to the serial interface is stopped. Then, the SCK pin is held high. At this time,
the IRQSIO flag (bit 3, address 3BH) of the register file is turned on (“1”).