參數(shù)資料
型號： UPD17201AGF
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCONTROLLER WITH LCD CONTROLLER/DRIVER AND A/D CONVERTER FOR INFRARED REMOTE CONTROL TRANSMITTERS
中文描述： 4位單片機與LCD控制器/驅(qū)動器和A / D轉(zhuǎn)換器紅外遙控遞質(zhì)
文件頁數(shù)： 72/120頁
文件大?。?/td> 516K
代理商： UPD17201AGF
μ
PD17201A, 17207
72
12. INTERRUPT FUNCTIONS
When a peripheral hardware unit (INT pin, 8-bit timer, clock timer, or serial interface) makes an interrupt request,
the interrupt function temporarily stops the execution of the current program and transfers program control to a
predetermined address (termed a vector address).
12.1
INTERRUPT SOURCES
The
μ
PD17207 supports the four interrupt sources (see Table 12-1).
When accepting an interrupt, the
μ
PD17207 automatically transfers program control to a predetermined address
(called a vector address).
Table 12-1 Vector Addresses
Priority
Interrupt Source
Vector Address
1
8-bit timer
(Internal)
0004H
2
Rising edge of INT pin input
(External)
0003H
3
Clock timer
(Internal)
0002H
4
Serial interface
(Internal)
0001H
If two or more interrupt requests are issued at the same time, the interrupt requests are accepted according to the
priorities assigned to them.
Accepting an interrupt is enabled or disabled by the EI or DI instruction. Basically, the interrupt is accepted when
it is enabled by the EI instruction. While the DI instruction is executed or while an interrupt is accepted, the other
interrupts are disabled.
To enable accepting another interrupt after one interrupt has been completed, the EI instruction must be executed
before the RETI instruction.
The interrupt is accepted by the EI instruction after the instruction next to EI has been executed; therefore, no
interrupt is accepted between the EI and RETI instructions.
12.2
HARDWARE OF INTERRUPT CONTROL CIRCUIT
This section describes the flags of the interrupt control circuit.
(1) Interrupt request flag and interrupt enable flag
The interrupt request flag (IRQxxx) is set to 1 when an interrupt request is generated, and is automatically
cleared to 0 when the interrupt processing is executed.
An interrupt enable flag (IPxxx) is provided to each interrupt request flag. When the IPxxx flag is 1, the interrupt
is enabled; when it is 0, the interrupt is disabled.
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