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參數(shù)資料
| 型號： | UPD16835AGS-BGG |
| 廠商： | NEC Corp. |
| 英文描述： | MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT |
| 中文描述： | 單片四H橋驅(qū)動電路 |
| 文件頁數(shù)： | 26/32頁 |
| 文件大?。?/td> | 227K |
| 代理商： | UPD16835AGS-BGG |
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Data Sheet S15973EJ1V0DS
26
μ
PD16835A
TIMING CHART (2)
H bridge ,
1ch output status
H bridge ,
2ch output status
(CW mode)
MOB
CLK
(PULSE OUT)
CLK
PULSE OUT
H bridge
1ch output status
H bridge
2ch output status
Position No.
1
2
3
CW
CW
4
5
6
5
CCW
CW
CW
CCW
4
3
2
3
CCW
CCW
CW
CW
4
Current direction: A1
A2
Current direction: B1
B2
CW mode
CCW mode
CW mode
Current direction: A2
A1
Current direction: B2
B1
Current direction: B2
B1
In CW mode
In CCW mode
(Expanded view)
β
β
Notes1.
: Position No. is incremented.
: Position No. is decremented.
Note1
Note1
Note2
2.
Remarks 1.
The current value of the actual wave is approximated to the value shown on the next page.
2.
The C
1
, C
2
, D
1
, and D
2
pins of
β
channel correspond to the A
1
, A
2
, B
1
, and B
2
pins of
α
channel.
3.
The CW mode is set if the D7 bit of the 2nd and 5th bytes of the standard data is
“
0
”
.
4.
The CCW mode is set if the D7 bit of the 2nd and 5th bytes of the standard data is
“
1
”
.
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