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參數(shù)資料
| 型號(hào)： | UPD16835AGS-BGG |
| 廠商： | NEC Corp. |
| 英文描述： | MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT |
| 中文描述： | 單片四H橋驅(qū)動(dòng)電路 |
| 文件頁數(shù)： | 20/32頁 |
| 文件大?。?/td> | 227K |
| 代理商： | UPD16835AGS-BGG |
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Data Sheet S15973EJ1V0DS
20
μ
PD16835A
(1)
(2)
(3)
Pulse width
Internal data retained.
Output reset
Not output
Rotation direction
Internal output retained
Not output
Number of pulses
Internal data retained.
Output reset
Not output
Updated to S2 data at FF2
Current setting
Internal output retained
Not output
ENABLE
Internal output retained
Not output
Updated to S2 data at either FF1 or FF2
by enable data of (2)
The initial mode of this product is as follows.
The IC operation can be initialized as follows:
(1) Turns ON V
DD
.
(2) Make RESET input
“
L
”
.
(3) Input serial initial data.
In initial mode, the operating status of the IC is as shown in Table 5-15.
Table 5-15. Operations in Initial Mode
Item
Specifications
Current consumption
100
μ
A
OSC
Oscillation stops.
Input of external clock is inhibited.
V
D
Input inhibited.
FF1 to FF7
“
L
”
level
PULSE OUT
“
L
”
level
EXP0 to EXP3
Undefined in the case of (1) above.
Previous value is retained in the case of (2) above.
Can be updated by serial data in the case of (3) above.
Serial operation
Can be accessed after initialization in the case of (1) above.
Can be accessed after RESET has gone
“
H
”
in the case of (2) above.
Can be accessed in the case of (3) above.
Step pulse output is inhibited and FF7 is made
“
L
”
if the following conditions are satisfied.
(1) If the set number of pulses (2nd/5th: standard data) is 00H.
(2) If the checksum value is other than 00H.
(3) If the start up wait time is set to 1 V
D
or longer.
(4) If the start up wait time + start up drive wait time is set to 1 V
D
or longer.
(5) If start up wait is completed earlier than LATCH (
↓
).
(6) If V
D
is not input.
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