參數(shù)資料
型號(hào)： TSPC860SRMZPU40D4
廠商： E2V TECHNOLOGIES PLC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 40 MHz, RISC PROCESSOR, PBGA357
封裝： PLASTIC, BGA-357
文件頁(yè)數(shù)： 84/90頁(yè)
文件大?。?/td> 2351K
代理商： TSPC860SRMZPU40D4
85
TSPC860
2129A–HIREL–08/02
Software Compatibility
Issues
The following list summarizes the major software differences between the TS68EN360
QUICC and the TSPC860 PowerQUICC:
Since the TSPC860 PowerQUICC uses an Embedded PowerPC Core, code written
for the TS68EN360 must be recompiled for the PowerPC instruction set. Code
which accesses the TS68EN360 peripherals requires only minor modifications for
use with the TSPC860. Although the functions performed by the PowerQUICC SIU
are similar to those performed by the QUICC SIM, the initialization sequence for the
SIU is different and therefore code that accesses the SIU must be rewritten. Many
developers of 68K compilers now provide compilers which also support the
PowerPC architecture.
The addition of the MAC function to the TSPC860 CPM block to support the needs
of higher performance communication software is the only major difference between
the CPM on the TS68EN360 and that on the TSPC860. Therefore the registers
used to initialize the QUICC CPM are similar to the TSPC860 CPM, but there are
some minor changes necessary for supporting the MAC function.
When porting code from the TS68EN360 CPM to the TSPC860 CPM, the software
writer will find new options for hardware breakpoint on CPU commands, address,
and serial request which are useful for software debugging. Support for single step
operation with all the registers of the CPM visible makes software development for
the CPM on the TSPC860 processor even simpler.
TSPC860 PowerQUICC
Glueless System Design
A fundamental design goal of the TSPC860 PowerQUICC was ease of interface to other
system components. Figure 72 on page 80 shows a system configuration that offers one
EPROM, one flash EPROM, and supports two DRAM SIMMs. Depending on the capac-
itance on the system bus, external buffers may be required. From a logic standpoint,
however, a glueless system is maintained.
Figure 73. TSPC860 System Configuration
Buffer
PRTY[3-0]
RAS
CAS[3-0]
W (write)
Data
Address
Parity
RAS
RAS2
RAS1
CAS[3-0]
PowerQUICC
MPC860
CS0
OE
Data
Address
CS7
WE[3-0]
CE (Enable)
OE (Output Enable)
WE (Write)
Data
Address
8-bit boot
EPROM
(Flash or Regular)
E (Enable)
G (Output Enable)
W (Write)
Data
Address
16 or 32 Bit
Two DRAM SIMMs
(Optional Parity)
8, 16 or 32-bit
SRAM
相關(guān)PDF資料
PDF描述
TSPC860SRMZPU50D4 32-BIT, 50 MHz, RISC PROCESSOR, PBGA357
TSPD11CGVRA0 PUSHBUTTON SWITCH, SPST, MOMENTARY, 0.02A, 20VDC, THROUGH HOLE-RIGHT ANGLE
2-1437573-9 PUSHBUTTON SWITCH, SPDT, MOMENTARY, 0.02A, 20VDC, SURFACE MOUNT-RIGHT ANGLE
3-1437573-4 PUSHBUTTON SWITCH, SPST, MOMENTARY, 0.02A, 20VDC, THROUGH HOLE-RIGHT ANGLE
TSPF5400AS21 5 mm, 1 ELEMENT, INFRARED LED, 870 nm
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