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參數(shù)資料
| 型號： | TSPC860SRMZPU40D4 |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 40 MHz, RISC PROCESSOR, PBGA357 |
| 封裝： | PLASTIC, BGA-357 |
| 文件頁數(shù)： | 18/90頁 |
| 文件大?。?/td> | 2351K |
| 代理商： | TSPC860SRMZPU40D4 |
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25
TSPC860
2129A–HIREL–08/02
Active Pull-up Buffers
Active pull-up buffers are a special variety of bidirectional three-state buffer with the fol-
lowing properties:
When enabled as an output and driving low, they behave as normal output drivers
(that is, the pin is constantly driven low).
When enabled as an output and driving high, drive high until an internal detection
circuit determines that the output has reached the logic high threshold and then stop
driving (that is, the pin switches to high-impedance).
When disabled as an output or functioning as an input, it should not be driven.
Due to the behavior of the buffer when being driven high, a pull-up resistor is required
externally to function as a ‘bus keep’ for these shared signals in periods when no drivers
are active and to keep the buffer from oscillating when the buffer is driving high,
because if the voltage ever dips below the logic high threshold while the buffer is
enabled as an output, the buffer will reactivate. Further, external logic must not attempt
to drive these signals low while active pull-up buffers are enabled as outputs, because
the buffers will reactivate and drive high, resulting in a buffer fight and possible damage
to the TSPC860, to the system, or to both.
Figure 6 compares three-state buffers and active pull-up buffers graphically in general
terms. It makes no implication as to which edges trigger which events for any particular
signal.
TRST
Pulled up
G19
Input
Reset for the scan chain logic. If JTAG is not used, connect TRST to
ground. If JTAG is used, connect TRST to PORESET. In case
PORESET logic is powered by the keep-alive power supply
(KAPWR), connect TRST to PORESET through a diode (anode
connected to TRST and cathode to PORESET).
SPARE[1-4]
Hi-Z
B7, H18,
V15, H4
No-connect
Spare signals — Not used on current chip revisions. Leave
unconnected.
Power Supply
See
Figure 4
Power
V
DDL — Power supply of the internal logic.
V
DDH — Power supply of the I/O buffers and certain parts of the clock
control.
V
DDSYN — Power supply of the PLL circuitry.
KAPWR — Power supply of the internal OSCM, RTC, PIT, DEC, and
TB.
V
SS — Ground for circuits, except for the PLL circuitry.
V
SSSYN, VSSSYN1 — Ground for the PLL circuitry.
Table 1. Signal Descriptions (Continued)
Name
Reset
Number
Type
Description
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