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參數(shù)資料
| 型號： | TSPC860SRMZPU40D4 |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 40 MHz, RISC PROCESSOR, PBGA357 |
| 封裝： | PLASTIC, BGA-357 |
| 文件頁數(shù)： | 19/90頁 |
| 文件大?。?/td> | 2351K |
| 代理商： | TSPC860SRMZPU40D4 |
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26
TSPC860
2129A–HIREL–08/02
Figure 6. Three-State Buffers and Active Pull-Up Buffers
Note:
Events 1 and 4 can be in quick succession.
Table 2 summarizes when active pull-up drivers are enabled as outputs.
The purpose of active pull-up buffers is to allow access to zero wait-state logic that
drives a shared signal on the clock cycle immediately following a cycle in which the sig-
nal is driven by the TSPC860. In other words, it eliminates the need for a bus turn-
around cycle.
Internal Pull-up and Pull-
down Resistors
The TMS and TRST pins have internal pull-up resistors. TSPC860 devices from Rev 0
to Rev A.3 (masks xE64C and xF84C) have an internal pull-up resistor on TCK/DSCK
but no internal pull-up resistor on TDI/DSDI. This was corrected on Rev B and later; on
these chips, the internal pull-up resistor was removed from TCK/DSCK and an internal
pull-up resistor was added to TDI/DSDI.
If RSTCONF is pulled down, during hardware reset (initiated by HRESET or PORE-
SET), the data bus D[0-31] is pulled down with internal pull-down resistors. These
internal pull-down resistors are to provide a logic-zero default for these pins when pro-
gramming the hard reset configuration word. These internal pull-down resistors are
disconnected after HRESET is negated.
No other pins have internal pull-ups or pull-downs.
1
2
3
12
35
4
1
Drive high on one edge
2
Switch to Hi-Z on later edge
3
Pull-up resistor maintains logic high state
1
Drive high on one edge
2
Switch to Hi-Z when threshold voltage
(Voh+margin) is reached
3
Pull-up resistor maintains logic high state
4
Disable buffer as output
5
Pull-up resistor maintains logic high state;
other driver can drive signal
Three-state
buffer
Active
pull-up
buffer
Table 2. Active Pull-Up Resistors Enabled as Outputs
Signal
Description
TS, BB
When the TSPC860 is the external bus master throughout the entire bus cycle.
BI
When the TSPC860’s memory controller responds to the access on the external bus, throughout the entire bus cycle.
TA
When the TSPC860’s memory controller responds to the access on the external bus, then:
For chip-selects controlled by the GPCM set for external TA, the TSPC860’s TA buffer is not enabled as an output.
For chip-selects controlled by the GPCM set to terminate in n wait-states, TA is enabled as an output on cycle (n-1) and
driven high, then is driven low on cycle n, terminating the bus transaction. External logic can drive TA at any point before
this, thus terminating the cycle early. [For example, assume the GPCM is programmed to drive TA after 15 cycles. If
external logic drives TA before 14 clocks have elapsed then the TA will be accepted by the TSPC860 as a cycle
termination.]
For chip-selects controlled by the UPM, the TA buffer is enabled as an output throughout the entire bus cycle.
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