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| 型號： | TSPC860SRMZPU40D4 |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 40 MHz, RISC PROCESSOR, PBGA357 |
| 封裝： | PLASTIC, BGA-357 |
| 文件頁數(shù)： | 6/90頁 |
| 文件大?。?/td> | 2351K |
| 代理商： | TSPC860SRMZPU40D4 |
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14
TSPC860
2129A–HIREL–08/02
GPL_A0
GPL_B0
High
D7
Output
General-Purpose Line 0 on UPMA — This output reflects the value
specified in the UPMA when an external transfer to a slave is
controlled by the UPMA.
General-Purpose Line 0 on UPMB — This output reflects the value
specified in the UPMB when an external transfer to a slave is
controlled by the UPMB.
OE
GPL_A1
GPL_B1
High
C6
Output
Output Enable — Output asserted when the TSPC860 initiates a
read access to an external slave controlled by the GPCM.
General-Purpose Line 1 on UPMA — This output reflects the value
specified in the UPMA when an external transfer to a slave is
controlled by UPMA.
General-Purpose Line 1 on UPMB — This output reflects the value
specified in the UPMB when an external transfer to a slave is
controlled by UPMB.
GPL_A(2-3)
GPL_B(2-3)
CS(2-3)
High
B5, C5
Output
General-Purpose Line 2 and 3 on UPMA — These outputs reflect
the value specified in the UPMA when an external transfer to a slave
is controlled by UPMA.
General-Purpose Line 2 and 3 on UPMB — These outputs reflect
the value specified in the UPMB when an external transfer to a slave
is controlled by UPMB.
Chip Select 2 and 3 — These outputs enable peripheral or memory
devices at programmed addresses if they are appropriately defined.
The double drive capability for CS2 and CS3 is independently
defined for each signal in the SIUMCR.
UPWAITA
GPL_A4
Hi-Z
C1
Bidirectional
User Programmable Machine Wait A — This input is sampled as
defined by the user when an access to an external slave is controlled
by the UPMA.
General-Purpose Line 4 on UPMA — This output reflects the value
specified in the UPMA when an external transfer to a slave is
controlled by UPMA.
UPWAITB
GPL_B4
Hi-Z
B1
Bidirectional
User Programmable Machine Wait B — This input is sampled as
defined by the user when an access to an external slave is controlled
by the UPMB.
General-Purpose Line 4 on UPMB — This output reflects the value
specified in the UPMB when an external transfer to a slave is
controlled by UPMB.
GPL_A5
High
D3
Output
General-Purpose Line 5 on UPMA — This output reflects the value
specified in the UPMA when an external transfer to a slave is
controlled by UPMA. This signal can also be controlled by the
UPMB.
PORESET
Hi-Z
R2
Input
Power on Reset — When asserted, this input causes the TSPC860
to enter the power-on reset state.
RSTCONF
Hi-Z
P3
Input
Reset Configuration — The TSPC860 samples this input while
HRESET is asserted. If RSTCONF is asserted, the configuration
mode is sampled in the form of the hard reset configuration word
driven on the data bus. When RSTCONF is negated, the TSPC860
uses the default configuration mode. Note that the initial base
address of internal registers is determined in this sequence.
HRESET
Low
N4
Open-drain
Hard Reset — Asserting this open drain signal puts the TSPC860 in
hard reset state.
Table 1. Signal Descriptions (Continued)
Name
Reset
Number
Type
Description
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