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參數(shù)資料
| 型號： | TSPC860SRMZPU40D4 |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 40 MHz, RISC PROCESSOR, PBGA357 |
| 封裝： | PLASTIC, BGA-357 |
| 文件頁數(shù)： | 82/90頁 |
| 文件大?。?/td> | 2351K |
| 代理商： | TSPC860SRMZPU40D4 |
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83
TSPC860
2129A–HIREL–08/02
System Interface Unit
(SIU)
The SIU on the TSPC860 PowerQUICC integrates general-purpose features useful in
almost any 32-bit processor system, enhancing the performance provided by the system
integration module (SIM) on the TS68EN360 QUICC device.
Although the Embedded PowerPC Core is always a 32-bit device internally, it may be
configured to operate with an 8-, 16- or 32-bit data bus. Regardless of the choice of the
system bus size, dynamic bus sizing is supported. Bus sizing allows 8-, 16-, and 32-bit
peripherals and memory to exist in the 32-bit system bus mode.
The SIU also provides power management functions, Reset control, PowerPC decre-
menter, PowerPC time base and PowerPC real time clock.
The memory controller will support up to eight memory banks with glueless interfaces to
DRAM, SRAM, SSRAM, EPROM, Flash EPROM, SRDRAM, EDO and other peripher-
als with two-clock access to external SRAM and bursting support. It provides variable
block sizes from 32 kilobytes to 256 megabytes. The memory controller will provide 0 to
15 wait states for each bank of memory and can use address type matching to qualify
each memory bank access. It provides four byte enable signals for varying width
devices, one output enable signal and one boot chip select available at reset.
The DRAM interface supports port sizes of 8, 16, and 32 bits. Memory banks can be
defined in depths of 256K, 512k, 1M, 2M, 4M, 8M, 16M, 32M, or 64M for all port sizes. In
addition the memory depth can be defined as 64K and 128K for 8-bit memory or 128M
and 256M for 32-bit memory. The DRAM controller supports page mode access for suc-
cessive transfers within bursts. The TSPC860 will support a glueless interface to one
bank of DRAM while external buffers are required for additional memory banks. The
refresh unit provides CAS before RAS, a programmable refresh timer, refresh active
during external reset, disable refresh modes, and stacking up to 7 refresh cycles. The
DRAM interface uses a programmable state machine to support almost any memory
interface.
PCMCIA Controller
The PCMCIA interface is a master (socket) controller and is compliant with release 2.1.
The interface will support up to two independent PCMCIA sockets requiring only exter-
nal transceivers/buffers. The interface provides 8 memory or I/O windows where each
window can be allocated to a particular socket. If only one PCMCIA port is being used,
the unused PCMCIA port may be used as general-purpose input with interrupt
capability.
Power Management
The TSPC860 PowerQUICC supports a wide range of power management features
including Full On, Doze, Sleep, Deep Sleep, and Low Power Stop. In Full On mode the
TSPC860 processor is fully powered with all internal units operating at the full speed of
the processor. A Gear mode is provided which is determined by a clock divider, allowing
the OS to reduce the operational frequency of the processor. Doze mode disables core
functional units other than the time base decrementer, PLL, memory controller, RTC,
and then places the CPM in low power standby mode. Sleep mode disables everything
except the RTC and PIT, leaving the PLL for lower power but slower wake-up. Low
Power Stop disables all logic in the processor except the minimum logic required to
restart the device, providing the lowest power consumption but requiring the longest
wake-up time.
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