參數(shù)資料
型號(hào)： TSPC860SRMZPU40D4
廠商： E2V TECHNOLOGIES PLC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 40 MHz, RISC PROCESSOR, PBGA357
封裝： PLASTIC, BGA-357
文件頁(yè)數(shù)： 46/90頁(yè)
文件大?。?/td> 2351K
代理商： TSPC860SRMZPU40D4
50
TSPC860
2129A–HIREL–08/02
Figure 28. Interrupt Detection Timing for External Edge Sensitive Lines
Notes:
1. PSST = 1. Otherwise add PSST times cycle time.
2. PSHT = 1. Otherwise add PSHT times cycle time.
These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA current
cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration.
CLKOUT
IRQx
I41
I42
I43
Table 10. PCMCIA Timing
Num
Characteristic
33 MHz50 MHz50 MHz66 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
P44
A(0:31), REG valid to PCMCIA Strobe
asserted
20.73
–
16.75
–
13
–
9.36
–
ns
P45
A(0:31), REG valid to ALE negation
28.30
–
23
–
18
–
13.15
–
ns
P46
CLKOUT to REG valid
7.58
15.58
6.25
14.25
5
13
3.79
11.84
ns
P47
CLKOUT to REG Invalid
8.58
–
7.25
–
6
–
4.84
–
ns
P48
CLKOUT to CE1, CE2 asserted
7.58
15.58
6.25
14.25
5
13
3.79
11.84
P49
CLKOUT to CE1, CE2 negated
7.58
15.58
6.25
14.25
5
13
3.79
11.84
ns
P50
CLKOUT to PCOE, IORD, PCWE, IOWR
assert time
11
ns
P51
CLKOUT to PCOE, IORD, PCWE, IOWR
negate time
2112
11
ns
P52
CLKOUT to ALE assert time
7.58
15.58
6.25
14.25
5
13
3.79
11.04
ns
P53
CLKOUT to ALE negate time
–
15.58
–
14.25
–
13
–
11.84
ns
P54
PCWE, IOWR negated to D(0:31) invalid
5.58
–
4.25
–
3
–
1.79
–
ns
P55
WAITA and WAITB valid to CLKOUT rising
edge
8
–
8
–
8
–
8
–
ns
P56
CLKOUT rising edge to WAITA and WAITB
invalid
2
–
2
–
2
–
2
–
ns
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