參數(shù)資料
型號(hào)： TS8388BCG
元件分類(lèi)： ADC
英文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72
封裝： CBGA-72
文件頁(yè)數(shù)： 6/46頁(yè)
文件大小： 499K
代理商： TS8388BCG
TS8388BG
14/46
4. PACKAGE DESCRIPTION.
4.1.
TS8388BG PIN DESCRIPTION
Symbol
Pin number
Function
GND
A2, A5, B1, B5, B10, C2,
C9, D2, E1,E2, E11, F1,
F2, G11, J3 , J9, K2 , K3,
K4, K5, K10, L2, L5
Ground pins.
To be connected to external ground plane.
VCC
A4, A6, B2, B4, B6, C3,
H1, H2, L6, L7
+5 V positive supply.
VEE
A3, B3, G1, G2, J1, J2
–5 V analog negative supply.
DVEE
F10, F11
–5 V digital negative supply.
VIN (Note 1)
L3
In phase (+) analog input signal of the Sample and Hold
differential preamplifier.
VINB (Note 1)
L4
Inverted phase (–) of analog input signal (VIN).
CLK (Note 1)
C1
In phase (+) ECL clock input signal. The analog input is
sampled and held on the rising edge of the CLK signal.
CLKB (Note 1)
D1
Inverted phase (–) of ECL clock input signal (CLK).
B0, B1, B2, B3, B4, B5,
B6, B7
A8, A9, A10, D10, H11,
J11, K9, K8
In phase (+) digital outputs.
B0 is the LSB. B7 is the MSB.
B0B, B1B, B2B, B3B,
B4B, B5B, B6B, B7B
B7, B8, B9, C11, G10,
H10, L10, L9
Inverted phase (–) Digital outputs.
B0B is the inverted LSB. B7B is the inverted MSB.
OR
K7
In phase (+) Out of Range Bit.
Out of Range is high on the leading edge of code 0 and
code 256.
ORB
L8
Inverted phase (+) of Out of Range Bit (OR).
DR
E10
In phase (+) output of Data Ready Signal.
DRB
D11
Inverted phase (–) output of Data Ready Signal (DR).
GORB
A7
Gray or Binary select output format control pin.
- Binary output format if GORB is floating or VCC.
- Gray output format if GORB is connected at ground (0 V).
GAIN
K6
ADC gain adjust pin.
The gain pin is by default grounded, the ADC gain transfer
function is nominally close to one.
DIOD/DRRB
K1
Die junction temperature measurement pin
And asynchronous Data Ready Reset active low, single ended
ECL input
VPLUSD
B11, C10, J10, K11
+2.4V for LVDS output levels otherwise to GND. Note 2
NC
A1, A11, L1, L11
Not connected.
Note 1 : No ESD protection.
Note 2 : The common mode level of the output buffers is 1.2V below the positive digital supply.
For ECL compatibility the positive digital supply must be set at 0V (ground ).
For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.
If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the posi-
tive digital supply level in the same proportion in order to spare power dissipation.
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