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參數(shù)資料
| 型號(hào)： | TS8388BCG |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
| 封裝： | CBGA-72 |
| 文件頁(yè)數(shù)： | 43/46頁(yè) |
| 文件大?。?/td> | 499K |
| 代理商： | TS8388BCG |
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TS8388BG
6/46
Parameter
Symb
Temp
Test
level
Min
Typ
Max
Unit
DIGITAL OUTPUTS (
notes 1,6)
Single ended or differential input mode, 50 % clock duty cycle (CLK,CLKB), Binary output data format,
Tj (typical) = 70
°C. Full temperature range :0 < Tc < +70°C.
Logic compatibility for digital outputs
( Depending on the value of VPLUSD )
(see Application Notes)
ECL or LVDS
Differential output voltage swings ( assuming
VPLUSD = 0V):
H 75 W open transmission lines ( ECL levels )
H 75 W differentially terminated
H 50 W differentially terminated
full
1.50
0.70
0.54
1.620
0.825
0.660
V
Output levels ( assuming VPLUSD = 0V)
75
W open transmission lines
(note 6)
H Logic ”0” voltage
VOL
25
°C
–1.62
–1.54
V
H Logic ”1” voltage
VOH
25
°C
–0.88
–0.8
V
Output levels ( assuming VPLUSD = 0V)
75
W differentially terminated
(note 6)
H Logic ”0” voltage
VOL
25
°C
–1.41
–1.34
V
H Logic ”1” voltage
VOH
25
°C
–1.07
–1
V
Output levels ( assuming VPLUSD = 0V)
50
W differentially terminated
(note 6)
H Logic ”0” voltage
VOL
25
°C
–1.35
–1.28
V
H Logic ”1” voltage
VOH
25
°C
–1.09
–1.02
V
Output level drift with temperature
full
1.6
mV/
°C
POWER REQUIREMENTS
Positive supply voltage
Analog
Digital (ECL)
VCC
VPLUS
IV
4.75
5
0
5.25
V
Digital (ECL)
Digital (LVDS)
VPLUS
D
0
2.4
V
Positive supply current
Analog
ICC
IV
400
425
mA
Digital
IPLUSD
120
130
mA
Negative supply voltage
VEE
Full
–5.25
–5
–4.75
V
Negative supply current
Analog
Digital
AIEE
DIEE
170
140
185
160
mA
Nominal power dissipation
PD
”
Full
3.6
3.8
3.7
3.9
W
Power supply rejection ratio
(note 2)
PSRR
+/– 0.5
mV/V
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| TS8388BCG | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72 |
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| TS8388BMFB/Q | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMFS | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
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