參數(shù)資料
型號: TS8388BCG
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72
封裝: CBGA-72
文件頁數(shù): 24/46頁
文件大?。?/td> 499K
代理商: TS8388BCG
TS8388BG
30/46
(TD1)
Time delay from
Data to Data Ready
TD1 is the time difference between Data to Data ready.
(TD2)
Time delay from
Data Ready to Data
General expression is TD1 = TC1 + TDR – TOD with TC = TC1 + TC2 = 1 encoding clock
period.
(TC)
Encoding clock
period
TC1 = Minimum clock pulse width (high) TC = TC1 + TC2
TC2 = Minimum clock pulse width (low)
(TPD)
Pipeline Delay
The number of clock cycles between the sampling edge of an input data and the
associated output data being made available, (not taking in account the TOD). For the
TS8388BG the TPD is 4 clock periods.
(TRDR)
Data Ready reset
delay
(To be completed).
(TR)
Rise time
20 % – 80% (To be completed).
(TF)
Full time
20 % – 80 % (To be completed).
(PSRR)
Power supply
rejection ratio
PSRR is the ratio of input offset variation to a change in power supply voltage.
(NRZ)
Non return to zero
When the input signal is larger than the upper bound of the ADC input range, the output
code is identical to the maximum code and the Out of Range bit is set to logic one. When
the input signal is smaller than the lower bound of the ADC input range, the output code
is identical to the minimum code, and the Out of range bit is set to logic one. (It is
assumed that the input signal amplitude remains within the absolute maximum ratings).
(IMD)
InterModulation Dis-
tortion
The two tones intermodulation distortion ( IMD ) rejection is the ratio of one of the two
input tone to the worst third order intermodulation products. The input tones levels are
at – 7dB Full Scale.
(NPR)
Noise Power Ratio
(to be defined)
相關(guān)PDF資料
PDF描述
TS8388BCG 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72
TS8388BCG 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72
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