參數(shù)資料
型號： TS8388BCG
元件分類： ADC
英文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72
封裝： CBGA-72
文件頁數(shù)： 2/46頁
文件大小： 499K
代理商： TS8388BCG
TS8388BG
10/46
Note 1 : Differential output buffers are internally loaded by 75
W resistors. Buffer bias current = 11 mA.
Note 2 : See definition of terms
Note 3 : Histogram testing based on sampling of a 10 MHz sinewave at 50 MSPS.
Note 4 : Output error amplitude < +/– 4 LSB around worst code.
Note 5 : Maximum jitter value obtained for single-ended clock input on the JTS8388B die (chip on board) : 200fs.
(500fs expected on TS8388BG)
Note 6 : Digital output back termination options depicted in Application Notes figures 3,4,5 .
Note 7 : With a typical value of TD = 465 ps, at 1 GSPS, the timing safety margin for the data storing using the ECLinPS 10E452
output registers from Motorola is of
± 315 ps, equally shared before and after the rising edge of the Data Ready signals (DR,
DRB).
Note 8 :The clock inputs may be indifferently entered in differential or single-ended, using ECL levels or 4 dBm typical power level into
the 50
W termination resistor of the inphase clock input.
(4 dBm into 50
W clock input correspond to 10 dBm power level for the clock generator.)
Note 9 :At 1GSPS, 50/50 clock duty cycle, TC2 = 500 ps (TC1). TDR – TOD =–100ps (typ) does not depend on the sampling rate.
Note 10 : Specified loading conditions for digital outputs :
– 50 ohms or 75 ohms controlled impedance traces properly 50 / 75 ohms terminated, or unterminated 75 ohms controlled
impedance traces.
– Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola.( e.g. : 10E452 ) ( Typical input
parasitic capacitance of 1.5 pF including package and ESD protections. )
Note 11 : Termination load parasitic capacitance derating values :
– 50 ohms or 75 ohms controlled impedance traces properly 50 / 75 ohms terminated : 60 ps / pF or 75 ps per additionnal
ECLinPS load.
– Unterminated ( source terminated ) 75 ohms controlled impedance lines : 100 ps / pF or 150 ps per additionnal ECLinPS
termination load.
Note 12 :apply proper 50 / 75 impedance traces propagation time derating values : 6 ps / mm (155 ps/inch) for TSEV8388BF Evalua-
tion Board.
Note 13 : Values for TOD and TDR track each other over temperature, ( 1 percent variation for TOD – TDR per 100 degrees Celsius
temperature variation ). Therefore TOD – TDR variation over temperature is negligible. Moreover, the internal ( onchip ) and
package skews between each Data TODs and TDR effect can be considered as negligible.Consequently, minimum values
for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced
Application Notes about TOD – TDR variation over temperature in section 7).
Note 14:Thermal resistance – junction to case :
Rthjc = 6.7
° C/W (typical value). With the use of an heatsink at a 2m/s air flow
speed, the Tc should not exceed 70deg.
相關PDF資料
PDF描述
TS8388BCG 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72
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相關代理商/技術參數(shù)
參數(shù)描述
TS8388BCGL 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays
TS8388BCGL (+LID) 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays
TS8388BMF 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays
TS8388BMFB/Q 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays
TS8388BMFS 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays
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