參數(shù)資料
型號: TRK-MPC5604P
廠商: Freescale Semiconductor
文件頁數(shù): 12/104頁
文件大?。?/td> 0K
描述: 5604P TTK BD
設(shè)計資源: TRK-MPC5604P Component List
TRK-MPC5604P Schematic
標準包裝: 1
系列: MPC56xx
類型: MCU
適用于相關(guān)產(chǎn)品: MPC5604P
所含物品: 板,線纜,CD,DVD
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
15
1.5.23
Serial communication interface module (LINFlex)
The LINFlex (local interconnect network flexible) on the MPC5604P features the following:
Supports LIN Master mode, LIN Slave mode and UART mode
LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications
Handles LIN frame transmission and reception without CPU intervention
LIN features
— Autonomous LIN frame handling
— Message buffer to store Identifier and as much as 8 data bytes
— Supports message length as long as 64 bytes
— Detection and flagging of LIN errors (sync field, delimiter, ID parity, bit framing, checksum, and time-out)
— Classic or extended checksum calculation
— Configurable Break duration as long as 36-bit times
— Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)
— Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection
— Interrupt-driven operation with 16 interrupt sources
LIN slave mode features
— Autonomous LIN header handling
— Autonomous LIN response handling
UART mode
— Full-duplex operation
— Standard non return-to-zero (NRZ) mark/space format
— Data buffers with 4-byte receive, 4-byte transmit
— Configurable word length (8-bit or 9-bit words)
— Error detection and flagging
— Parity, Noise and Framing errors
— Interrupt-driven operation with four interrupt sources
— Separate transmitter and receiver CPU interrupt sources
— 16-bit programmable baud-rate modulus counter and 16-bit fractional
— 2 receiver wake-up methods
1.5.24
Deserial serial peripheral interface (DSPI)
The deserial serial peripheral interface (DSPI) module provides a synchronous serial interface for communication between the
MPC5604P MCU and external devices.
The DSPI modules provide these features:
Full duplex, synchronous transfers
Master or slave operation
Programmable master bit rates
Programmable clock polarity and phase
End-of-transmission interrupt flag
Programmable transfer baud rate
Programmable data frames from 4 to 16 bits
Up to 20 chip select lines available
— 8 on DSPI_0
— 4 each on DSPI_1, DSPI_2 and DSPI_3
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