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參數(shù)資料
| 型號： | TPS56100PWPR |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Voltage-Mode SMPS Controller |
| 中文描述： | 電壓模式開關(guān)電源控制器 |
| 文件頁數(shù)： | 12/34頁 |
| 文件大小： | 811K |
| 代理商： | TPS56100PWPR |
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A
–
MARCH 2000
–
REVISED OCTOBER 2000
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics T
J
= 0
°
to 125
°
C, V
CC
= 2.8 V to 5.5 V (unless otherwise noted) (continued)
V
SENSE
–
RR
and V
SENSE
–
LDO
discharge
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VSENSE
–
RR discharge FET current saturation
VSENSE
–
RR discharge series resistance (limits current)
VSENSE
–
RR discharge FET propagation delay time
VSENSE
–
LDO discharge FET current saturation
VSENSE
–
LDO discharge series resistance (limits current)
VSENSE
–
LDO discharge FET propagation delay time
NOTE 2. Ensured by design, not production tested.
VSENSE
–
RR = 1.5 V,
INHIBIT = 0 V,
See Note 2
5
mA
k
ns
VIN = 5.5 V
1
See Note 2
100
VSENSE
–
LDO = 3.3 V,
INHIBIT = 0 V,
See Note 2
5
mA
k
ns
VIN = 5.5 V,
1
See Note 2
100
detailed description
reference/voltage identification
The reference/voltage identification definition (VID) section consists of a temperature compensated bandgap
reference and a 2-pin voltage selection network. Both ripple regulator and LDO reference voltages are
programmed with each VID setting. The 2 VID pins are inputs to the VID selection network and are tri-level inputs
that may be set to GND, floating (V
BIAS
/2), or V
BIAS
.
The VID codes allow the controller to power both current
and future DSP products. The output voltages may also be programmed by external resistor voltage dividers
for any values not included in the VID code settings. Refer to Table 1 for the VID code settings. The output
voltages of the VID network, V
REF
–
RR
, is within 1.5% and V
REF
–
LDO
is within 2.5% of the nominal setting over
the VID range of 1.3 V to 3.3 V. The reference tolerance conditions include a junction temperature range of
–
40 C to +125 C and a V
CC
supply voltage range of 2.8 V to 5.5 V. The V
REF
–
RR
output of the reference/VID
network is indirectly brought out through a buffer to the VREFB pin. The voltage on this pin will be within 1.5%
of V
REF
–
RR
. It is not recommended to drive loads with VREFB, other than setting the hysteresis of the hysteretic
comparator, because the current drawn from VREFB sets the charging current for the slow-start capacitor. Refer
to the slow-start section of this document for additional information.
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by 2 external resistors and is centered around V
REF
. The two external resistors form a resistor divider from
VREFB to ANAGND, and the divided down voltage connects to the VHYST pin. The hysteresis of the
comparator will be equal to twice the voltage difference that is across the VREFB and VHYST pins. The
propagation delay from the comparator inputs to the driver outputs is 250 ns maximum. The maximum
hysteresis setting is 60 mV.
low-side driver
The low-side driver is designed to drive low r
DS(on)
logic-level N-channel MOSFETs. The current rating of the
driver is 2-A typical, source and sink. The bias to the low-side driver is internally connected to the regulated
synchronous charge pump output.
high-side driver
The high-side driver is designed to drive low r
DS(on)
logic-level N-channel MOSFETs. The current rating of the
driver is 2 amps typical, source and sink. The high-side driver can be configured either as a floating bootstrap
driver or as a ground-reference driver. When configured as a floating driver, the bias voltage to the driver is
developed from the charge pump VDRV voltage. The internal synchronous bootstrap rectifier, connected
between the VDRV and BOOT pins, is a synchronously-rectified MOSFET for improved drive efficiency. The
maximum voltage that can be applied between the BOOT pin and ground is 14 V.
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