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參數(shù)資料
| 型號(hào)： | TP6508 |
| 英文描述： | Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT |
| 中文描述： | 顯卡 |
| 文件頁(yè)數(shù)： | 72/134頁(yè) |
| 文件大小： | 600K |
| 代理商： | TP6508 |
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P.69
Extended Indexed Register CREG A3 : Panel Miscellaneous Control Register 4
This is a read/write register.
Port address is Hex 3D5.
Default value after hardware reset is Hex 00.
D0
D1
D2
D3
D4
D5
D6
D7
Enable vertical expansion for text mode
Enable vertical expansion for graphic mode
Force 8 dots character clock
Enable shadow frame buffer with internal Line buffer for Mono Dual-scan STN LCD
Enable shadow frame buffer with internal Line buffer for Color Dual-scan STN LCD
Enable external frame buffer for Color Dual-scan STN LCD
Enable extra LLCLK 244
Enable extra LLCLK 242
Bit 0
Bit 1
Bit 2
A logical 1 forces TP6508 to fit the panel vertical resolution for text mode.
A logical 1 forces TP6508 to fit the panel vertical resolution for graphic mode.
In panel mode , LCD and PLASMA manufactures produce 640x480 pixel panel . Some IBM standard
modes define 9 dots per character , all characters cannot display 80 columns (720 dots) at the same
time . When this bit is a logical 1, TP6508 force character width to be 8 dots.
In monochrome dual-scan STN LCD display,logical 1 enables shadow frame accelerate operation. At
this time, TP6508 can gain better display quality and up to 64 gray level. Other flat panel display
modes this bit is invaild .
In color dual-scan STN LCD display,logical 1 enables shadow frame accelerate operation. At this
time, TP6508 can gain better display quality and up to 64k color
modes this bit is invaild .
In color dual-scan STN LCD display, logical 1 enables external frame accelerate operation to gain
better display quality. At this time an extra DRAM(s) is necessary . A logical 0 disables the external
frame buffer and TP6508 uses the Pseudo Frame Buffer technique to implement the display mode .
Other display mode this bit is invaild .
A logical 1 enables one extra LLCLK for LCD monochrome panels that require 244 line clocks for
the upper panel.
A logical 1 enables one extra LLCLK for LCD monochrome panels that require 242 line clocks for
the upper panel.
Bit 3
Bit 4
level . Other flat panel display
Bit 5
Bit 6
Bit 7
Extended Indexed Register CREG A4 : LCD AC Modulation Period Register
This is a read/write register.
Port address is Hex 3D5.
Default value after hardware reset is Hex 00.
D0-7 LCD AC modulation bit 0 to 7
Bit 0-7
AC modulation LCD panel cannot be driven in the DC level. Some LCD panel modules
do not provide AC modulation signal, TP6508 offers this function to prevent LCD
damage. These bits define the number of LP(Hsync) between adjacent phase changes on
MOD output. As these bits are programmed to hex 00, then the MOD signal phase
changes every frame.
Extended Indexed Register CREG A5 : Panel Miscellaneous Control Register 5
This is a read/write register.
Port address is Hex 3D5.
Default value after hardware reset is Hex 00.
D0
Panel resolution selection
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